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TPS62874-Q1: Webench design and analysis

Part Number: TPS62874-Q1
Other Parts Discussed in Thread: TPS62870, TPS62869, TPS62870-Q1,

Tool/software:

In design phase of an ASIC validation test board and considering the TPS62874 for the core voltage regulator. Application is 3.3 VIN, 0.5-0.55 VOUT @ 2-3A. Maximum efficiency is important. Given the current requirements, the TPS62870 or x71 devices would be acceptable. However, the x74 seems to provide more efficiency (approximately 40 mW better) at the above operating point. I have a few questions that I would appreciate help with.

1). Comparing data sheet application curves from TPS62870-73 (10.2.3) vs. TPS62874-77 (9.2.3) there is an implication that the x71 for example is more efficient at our desired operating point. However, using a Webench based design comparison the x74 is more efficient as mentioned above. As a baseline i tried to determine the discrepancy between Webench and the data sheets. For a 3.3 VIN, 0.75 @ max device current a x73 design seems to match Fig 10-6 of the data sheet whereas the x77 design efficiency chart seems to be high by about 2-4 % (depending on current) from the Fig 9-5 x77 data sheet. Can you please verify my understanding and if there is a real discrepancy between Webench analysis and the data sheet? I am targeting the x74 for selection based on efficiency although the droop compensation feature might be of benefit as well.

2) The x74-77 family seems to share the same basic CMC architecture with the x70-73 family. However, some of the design formulas for component selection have differences between the "Typical Application". Can you confirm that the differences are intentional and that the Webench design is using these equations? One parameter of interest is what is Webench using for load step? Is it the maximum current? Also, for the x74 device there was a statement in 8.3.7.5 of its' data sheet implying the output capacitance can be reduced if droop compensation is enabled. Does the Webench based design take droop compensation into account?

3) Input current measurement will be required for the given ASIC rail under test. Initially was hoping to use the inductor DCR current sense method but it appears that the combination of low DCR for the recommended inductors and also DCR tolerance will result in insufficient measurement accuracy. Proposing to add a discrete 10 mohm sense resistor in series with the inductor before the output capacitors. From the PSPICE simulation for the x74 device (average transient model) it appears that the only impact of the sense resistor is to extend the settling time after a load step by ~10 us. This should be ok for our application. I can envision the sense resistor addition won't be ideal from a layout perspective as it seems like the output capacitors might need to sit further away from the IC. Can you comment on any negative impact such as to layout or otherwise to consider?

Thank you very much for your time and consideration.

  • Hello Sam,

    Thanks for reaching out to us.

    Before we go into detailed discussion on your application, do you need Automotive-grade device? If not, you might like to consider TPS62868x which can reached 85% to 87.5% efficiency at 2A to 3A load (Vout = 0.6V). The device can also operate at low as 0.4V. Let me know your thoughts

    DS: https://www.ti.com/lit/ds/symlink/tps62869.pdf?ts=1717488979076&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTPS62869

    Best regards,

    Excel

  • Hi Excel,

    Thank you for the prompt reply. Sorry, for my delayed response. I was expecting an email notification but that did not seem to work with your reply. Regarding Automotive grade, strictly speaking we only need the temp range that an auto grade provides. However, the application can afford the slight cost premium with the auto grade device, given the more comprehensive data provided for reliability analysis. We are developing an evaluation board for both an ASIC and the POL regulator subsystem that will likely be implemented in a mass produced module.

    Regarding, the suggested device, the TPS62869, there are 2 issues from our application perspective. Although we don't require stacked regulator operation, we want the option to sync regulators for hopefully EMI minimization. Moreover, i did a Webench for both the TPS62874 and the TPS62869 with the following: 

    Input: 
    DC 3.2 V - 3.4 V
    Output: 
    0.5 V at 3 A
    And the TPS62874 dissipates 180 mW at 3A and TPS62869 dissipates 271 mW at 3A from their respective Webench circuit generation and analysis. Maximum efficiency is very important in our application. I am using the Webench generated circuits for comparison with the expectation that they should give accurate data at our operating points (which may or may not be in the data sheets) and also match the data sheets for those operating points that were tested.
    My original question 1) pertains to the accuracy for the Webench vs. the data sheet.
    Thank you,
    Sam
  • Hi Sam, 

    Thanks for the clarification. TPS6287x-Q1 offers better efficiency at 3A and above load. By the way, only TPS62870-Q1 have the 0.5V default output voltage version while TPS62874/5/6/7-Q1 doesn't have it.

    To address your previous queries, please refer to the comments below.

    1). Comparing data sheet application curves from TPS62870-73 (10.2.3) vs. TPS62874-77 (9.2.3) there is an implication that the x71 for example is more efficient at our desired operating point. However, using a Webench based design comparison the x74 is more efficient as mentioned above. As a baseline i tried to determine the discrepancy between Webench and the data sheets. For a 3.3 VIN, 0.75 @ max device current a x73 design seems to match Fig 10-6 of the data sheet whereas the x77 design efficiency chart seems to be high by about 2-4 % (depending on current) from the Fig 9-5 x77 data sheet. Can you please verify my understanding and if there is a real discrepancy between Webench analysis and the data sheet? I am targeting the x74 for selection based on efficiency although the droop compensation feature might be of benefit as well.

    To answer your question about the efficiency accuracy, please consider the datasheet because it is based on actual bench evaluation, while Webench result was derived from mathematical calculation. TPS62870-Q1 should offer slightly better efficiency at light load due to lower switching losses compared to TPS62874-Q1 which is optimized at a higher load. (Note: switching losses are more dominant at lower load, while conduction losses (FET RDSon) contributes heavily at higher load current).

    2) The x74-77 family seems to share the same basic CMC architecture with the x70-73 family. However, some of the design formulas for component selection have differences between the "Typical Application". Can you confirm that the differences are intentional and that the Webench design is using these equations? One parameter of interest is what is Webench using for load step? Is it the maximum current? Also, for the x74 device there was a statement in 8.3.7.5 of its' data sheet implying the output capacitance can be reduced if droop compensation is enabled. Does the Webench based design take droop compensation into account?

    Both devices uses the same control scheme, however there were some variations in terms of implementation and features. So, the difference in the calculations for component selections were expected due to the variance in design parameters. For load step simulation, the load current deviation can be clicking the current source symbol in the schematic diagram. See figures below for details.

    Another possible option to simulate the transient response is to use the Simplis model (https://www.ti.com/product/TPS62870-Q1#design-tools-simulation)

    1. Go to Simulate window and select the "Load Transient" option 

    2.  Click the "Iout" symbol in the schematic diagram to edit the transient load parameters

    3. Click the "Start" button to initiate the simulation

    The "Simulate" function of TPS62874-Q1  is not enabled in Webench. So, I cannot confirm if the droop compensation function is working. Anyway, you can also use the Simplis model to check the device behavior with or without droop compensation (https://www.ti.com/product/TPS62874-Q1#design-tools-simulation). 

    3) Input current measurement will be required for the given ASIC rail under test. Initially was hoping to use the inductor DCR current sense method but it appears that the combination of low DCR for the recommended inductors and also DCR tolerance will result in insufficient measurement accuracy. Proposing to add a discrete 10 mohm sense resistor in series with the inductor before the output capacitors. From the PSPICE simulation for the x74 device (average transient model) it appears that the only impact of the sense resistor is to extend the settling time after a load step by ~10 us. This should be ok for our application. I can envision the sense resistor addition won't be ideal from a layout perspective as it seems like the output capacitors might need to sit further away from the IC. Can you comment on any negative impact such as to layout or otherwise to consider?

    Based on my experience, placing a current resistor along the output rail impacts the transient performance of the converter (higher overshoot/undershoot and poor loop stability). But this can be optimized by decreasing the the capacitor placed close to the buck converter and move majority of the Cout near the load. This can be validated in using the Simplis model.

    Best regards,

    Excel

  • Thank you Excel, I have been persuaded to use the TPS62870 in this application. Please close the case.

    Sam Barsamian