TPS6594-Q1: Safety Manual: [SA_11] The MCU will put the system in a safe state when the TPS6594-Q1 resets the SoC.

Part Number: TPS6594-Q1
Other Parts Discussed in Thread: TDA4VL

Tool/software:

Dear TI support team, 

I would like to ask about the assumption SA_11 in the safety manual which states that: 

The MCU will put the system in a safe state when the TPS6594-Q1 resets the SoC.

What is meant here by MCU? Is it the TDA4VL safety domain taking into consideration that the PMIC is power supply provider of TDA4? 

Thanks in advance, 

Best Regards

Ahmad

  • The MCU will put the system in a safe state when the TPS6594-Q1 resets the SoC.

    What is meant here by MCU? Is it the TDA4VL safety domain taking into consideration that the PMIC is power supply provider of TDA4? 

    When TPS6594133A is used in a split power group scenario, if a fault on an SOC grouped rail the PMIC will set the nRSTOUT_SOC pin low and power down rails in the SoC power group. The MCU safety island would then have to clear the interrupts before turning the SoC rails back on. 

    The MCU supplies are depicted in Figure 2-1 of the TPS6594133A user guide: https://www.ti.com/lit/pdf/slvuci2

  • Hello, 

    As per our use case, TPS65941213 and LP876411B4 PMICs are used for for J721E (PDN-1A). 

    As far as I understand, the entire SoC is in a single power group. 

    Could you please confirm if such assumption needs to be fulfilled as per our use case?

    Thanks in advance, 

    Best Regards

  • Could you please confirm if such assumption needs to be fulfilled as per our use case?

    Yes it still needs to be fulfilled.

    A WD_ERROR or ESM_MCU_ERROR will cause warm reset. Both the nRSTOUT and nRSTOUT_SOC pins will be toggled low and then high. The EN_DRV pin is driven low. After warm reset occurs, the MCU needs to restart the watchdog and handle the EN_DRV. PMIC output rails do not power down during a warm reset.