TPS65219: 1V8 Feedback on VDD_1V2 (Buck3) rails on startup

Part Number: TPS65219

Tool/software:

Hi,

We are currently designing the AM6254 SoC onto a new module using the TPS6521903 PMIC to power the SoC. During the power-up sequence the rails ramp up as defined in SLVUCJ2 up to Buck3 (1V2), then the PMIC powers down and retries 2 more times before shutting down completely. Measuring the Buck3 (1V2) rail showed that it is getting 1V8 fed back on the rail before the rail should be activated causing the PMIC to halt, retry, and finally terminate the power-up sequence.

Please see the linked post, am625-vdd_1v8-vdda_1v8-feedthrough-on-vdd_1v2-rails-on-startup on the processor forum for more detail and various attempts that have been made to find the problem.

Any insight would be appreciated.

  • Hi,

    Thank You for using E2E. If the PMIC rails are disconnected from the load, does it execute the full power-up sequence?

    Could you share the schematic in a searchable PDF?

    Thanks,

    Brenda

  • Hi Brenda,

    Yes, with the SoC removed the rails all come up in sequence. I have attached the schematics as requested.

    Kind regards,

    Christiaan


    SOM-001001-000-SCH.pdf

  • Thank You for sharing the schematic. I'll take a look and provide feedback within the next 24-48Hrs.

    Thanks,

    Brenda

  • Hi Christiaan,

    Thank You for your patience. I took a look at the schematic and noticed the PMIC VSEL_SD pin is missing the external pull-up or pull-down resistor that defines the initial pin state and set the LDO1 output voltage at startup. The VSEL_SD pin on the TPS6521903 is configured to set the output voltage on LDO1 with the following polarity: 

    • VSEL_SD HIGH, LDO1=3.3V (requires 3.3V on PVIN_LDO1)
    • VSEL_SD LOW, LDO1=1.8V

    The other thing I noticed was that RESETSTATz is missing the external 10K pull-down that Sitara recommends to keep the RESET pin low until the SoC is out of reset and during power-up. 

    Thanks,

    Brenda

  • Hi Brenda,

    Thanks for taking the effort.

    I have pulled the RESETSTATz pin low, no change to the fault. The VSEL_SD pin I have pulled high (LDO1 = 3V3) and low (LDO1=1V8), the fault remains the same though.

    Thanks,

    Christiaan

  • Hi Christiaan,

    If you fixed the two items highlighted in my previous email and the PMIC is able to successfully execute the power-up sequence when the load is disconnected, then the issue might not be PMIC related. Here are my next questions:

    • For how long does the PMIC stay ON after the nRSTOUT goes high?

    • Could you share a scope capture of all the PMIC rails turning OFF? Please use a small time scale so we can see who is the first rail turning OFF.

    • After the PMIC shutdown the first time, on the second attempt (before it shutdown again) could you read the PMIC interrupt register (i.e. address 0x2B)?  

    • Could you measure or scan the thermals in the PMIC area? You could use a thermal camera or any other method so see if the PMIC is triggering a thermal shutdown. 

    • Have you captured the output current? I would like to understand what specific fault that is causing the PMIC to shutdown. It could be current limit, thermal shutdown, etc.

    • Does the PMIC enable pin always stay high?

    Thanks,

    Brenda

  • Hi Brenda,

    To answer your questions:

    1) With the SoC in circuit the nRSTOUT pin never goes high. According to SLVUCJ2 Figure 2-1; nRTSOUT only goes high after the SoC oscillator has started up. The PMIC shuts down way before that when it tries to start up BUCK3. With the SoC removed the PMIC behaves as expected.

    2) I have attached scope images a) start-up, b) first turn-off, c) entire power up sequence. Please note: 3V3 is sourced from the U10 buck converter, 1V8 is the BUCK2, LDO1/LDO3/LDO4 all come up within 1ms of BUCK2, 1V2 is supposed to be the BUCK3 rail, BUCK1/LDO2 never come up.

    3) I will have to get back to you on this. I'll have to wire in a TPS65219 dev board.

    4) Thermal camera doesn't pick up any significant heat being generated but the PMIC is also only on for 100 ms and I don't have a high enough frame rate camera to pick up anything useful.

    5) Will measure via TPS65219 dev board.

    6) Yes.

    Kind regards,

    Christiaan

  • Thanks for providing the captures. I'll review and provide feedback within 24-48Hrs.

  • Thanks for your patience. I see Buck3 output voltage is higher than 1.2V. When the SoC is connected, there seems to be a backfeeding issue that is forcing a voltage close to 1.8V on Buck3. PMIC is expected to wait ~3ms after Buck2 to turn-ON Buck3. 

    This seems to be an issue with the DDR routing. Could you share the schematic for the DDR?

    Thanks,

    Brenda

  • Hi Brenda,

    The DDR schematic is on page 4 of the attached document.

    Kind regards,

    Christiaan

    2870.SOM-001001-000-SCH.pdf

  • Christiaan,

    I was not able to identify a path that on the DDR schematic that would explain the backfeeding issue. If the PMIC works as expected after disconnecting the load from the output rails, then I would recommend continuing the investigation with the processor team. 

    Thanks,

    Brenda