TPS65987DDJ: PD I2C timing fall time is less than spec

Xu jinhao

Part Number: TPS65987DDJ

Tool/software:

PD chip as slave, the I2C clk frequency is about 349.8 KHz, fall time is measured about 2 ns, while the spec tOCF is 12~250 ns, is that ok for TBT3 dock design?

Attached the screenshot for reference, please have a check, thanks a lot.

4 months ago

0 Tommy Lin 4 months ago

TI__Mastermind 22080 points

Hi,

Please keep in mind that the I2C bus capacitance will affect the fall time. Seems like the capacitance on the bus might be on the lower end, do you know the capacitance of your I2C bus?

Regards

0 Xu jinhao 4 months ago

Prodigy 10 points

Hi Tommy,

Appreciated for your reply, no a capacitor on the I2C bus, maybe is there no high risk for fall time less than spec? Looking forward to your reply again, thanks.

+1 Tommy Lin 4 months ago in reply to Xu jinhao

TI__Mastermind 22080 points

Hi,

I am referring to the capacitance of the trace but yes I believe the fall time should not have that big of an impact since data is sampled at the SCL line rising edge.

Regards

0 Xu jinhao 4 months ago in reply to Tommy Lin

Prodigy 10 points

Hi Tommy,

Thanks a lot, Do you mean the trace parasitic capacitance, we will synchronously check it. Appreciated for your reply!

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TPS65987DDJ: PD I2C timing fall time is less than spec