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Original question:

DRV8320R: design and brakes questions

CSD88599Q5DC: Can unified mosfet used on buck converters?

Fong Brian
Prodigy 60 points
Part Number: CSD88599Q5DC

Tool/software:

Dear TI,

I am puzzled by TI unified mosfet product is not suggested on buck converter.

WEBENCH also do not propose any kind of unified NMOS array as well.

So what is the major concern on such lower inductance and better cascode NMOS.

Bests,

Brian

  • 0
    TI__Mastermind 31605 points

    Hello Brian,

    Thanks for your interest in TI FETs. The CSD88599Q5DC was designed and optimized for low frequency (up to 50kHz) motor drive applications. It has not been evaluated for synchronous buck applications and is not recommend for this application. The stack up of the device is different from TI's power blocks optimized for sync buck. The high side FET in the half bridge is on the bottom with its drain connected to the thermal pad (VIN) on the underside of the package. The low side FET is on the top with its source connected to the PGND pins. This arrangement works well in motor drive but is not optimal for sync buck due to the higher source inductance of the low side FET. This could cause cross conduction at higher switching frequencies. 

    If you can share your requirements, I can help identify a more appropriate device for your application.

    Best Regards,

    John Wallace

    TI FET Applications

  • 0 in reply to John Wallace1
    Prodigy 60 points

    Dear Wallace,

    Appreciate the explanations and suggestions.

    Yes I would like more info on the buck fets.

    Lets say the requirement is 200khz or below and 60V VDS low RDS and Cgtot should control at 25-40nC.

    Bests,

    Brian

  • 0 in reply to Fong Brian
    TI__Mastermind 31605 points

    Hi Brian,

    TI has an Excel-based FET selection tool at the link below. This allows the user to input their requirements and compared up to 3 different TI FET solutions. Please give it a try and let me know if you run into any problems.

    https://www.ti.com/tool/SYNC-BUCK-FET-LOSS-CALC

    Thanks,

    John

  • 0 in reply to John Wallace1
    Prodigy 60 points

    Hi John,

    During experiment from theory to actual implementation the efficiency of the CSD88599 indeed is better than splitted NMOS configuration.

    Less inductance means less ringing and power losses Ldi/dt.

    So I cannot see why TI is not proposing such better mosfet on buck converter.

    I am going to also ask more question about CSD88599 on top of this ticket which should be related.

    The top thermal pad as you had explained is GND and bottom thermal pad is VIN.

    But even when such mosfet is applied to motor design the GND top pad cannot be mounted to heat sink w/o isolation.

    This is due to shunt resistor configuration so no matter the top is VIN or bottom is GND the heat sink itself cannot directly mount onto the mosfet.

    So I am not sure why this mosfet is not acceptable for half bridge application like sync-buck?

    Would you mind to explain a bit more.

    Bests,

    Brian

  • 0 in reply to John Wallace1
    TI__Mastermind 31605 points

    Hi Brian,

    I do not see your last response on this thread although I received an email from the system with it. As I stated previously, the CSD88599Q5DC was optimized for motor drive applications with PWM frequency < 50kHz and as such, it has not been tested in a synchronous buck converter. Also, it has only been tested up to 50kHz switching frequency. If you decide to use the device in a sync buck, TI cannot guarantee the performance as we have no supporting data in that application. I would recommend thoroughly testing the device to make sure the performance is acceptable. Pay special attention to SW node waveforms to make sure the voltage does not exceed BVDSS for the power block. Please review the app note at the link below on ringing reduction techniques for sync buck converters. You should include spots for gate resistors, R-C snubber from SW node to GND and a resistor in series with the boot capacitor for the MOSFET gate driver.

    You are correct that a heat sink cannot be directly attached to the exposed metal slug on the topside of the package. Normally, a thermal interface material (electrically insulating/thermally conducting) is applied between the device and heat sink because the surface is not completely flat.

    https://www.ti.com/lit/an/slpa010/slpa010.pdf

    I'll see what additional information I can find on using (or not using) this device in a sync buck application.

    Best Regards,

    John

  • 0 in reply to John Wallace1
    Prodigy 60 points

    Hi John,

    Appreciate the enclosed document well read and indeed explained sync-buck design 101.

    Which I should be learn decade ago.

    On top of that all snubber bootstrap resistor or gate resistor is to optimize the EMI and reduce the VDS mosfet selection in summary.

    So efficiency point of view is completely not even considered. All the major losses are SW-freq selection Inductor and the RDS on.

    So when these 3 elements are well tuned the only last we can do is the layout itself as the switching length indeed contribute losses as the document also proposed.

    So power block aka unified half-bridge NMOS is what sync-buck needed.

    But as far I know the market is not providing too much options.

    Bests,

    Brian

  • +1 in reply to Fong Brian
    TI__Mastermind 31605 points

    Hi Brian,

    The added EMI mitigation components may or may not be required depending on how much overshoot and ringing is seen on the SW node waveform. They may end up being no stuff or 0 ohm resistors. All of these circuit methods dissipate additional power and reduce the efficiency. TI has many power block FET solutions but the majority of the products are lower voltage (25V or 30V). The power block product selection is limited to only 2 devices >= 40V and both are optimized for motor drive solutions. Our low voltage power block products are optimized for sync buck converters and are typically higher performance than discrete solutions because of the reduce parasitic inductance. As always, PCB layout is critical to achieve the best performance. For future reference, the app note at the link below includes links to all of TI's web based FET technical information. Let me know if there is anything else I can do to help you.

    https://www.ti.com/lit/an/slvafg3f/slvafg3f.pdf

    Thanks,

    John