UCC21710-Q1: HOW TO CALCULATE THE VALUE OF THE SHUNT RESISTANCE IN THE BELOW SCHEMATIC (R2 AND R14)

Hi Upender,

Please find the following FAQ on the recommended schematic and layout for UCC21710-Q1 devices,

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1377445/faq-ucc21710-q1-schematic-and-layout-recommendation

As you notice that we don't need a parallel resistor for DESAT decap. I am curious why do you plan it?

Thanks

Sasi

Hi Upender - Posting your questions in this thread as the other thread is FAQ.

Kindly clear below point

1. above schematic and layout  are for  deset (desaturation calculation ) this is ok  for this information .

2. i need Rshunt calculation instant deset with any devices example .

3. Suggest capacitor value of power supply input and output side enclose data sheet of isolated power supply dc-dc (DTAT SHEET ENCLOSED)

4. Please give schematic and layout for AIN & APWM

IGBT Driver QA151&121CX Datasheet （REV-A0 2021-11-29）.pdf

 point 3 need to suggest input & output capacitor before Bypass capacitor ( use Bypass capacitor near the power supply pin 104pf & 105pf  X7R PAKAGE 1210 ),  i am using 4 layer pcb bypass capacitor place  in  bottom side pcb on pin  < 2mm  it is ok ?

2. Can you please suggest, what is the purpose of Rshunt?

3. For the gate driver, the FAQ added have the details of the VCC and VDD power supply pins recommendation  required decoupling capacitor values. Bias recommendation need to be followed based on its datasheet and ensure that input, output capacitance follows the recommended value per its datasheet.

4. AIN , APWM schematic recommendation and example circuit is given in the FAQ link, 

 https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1377445/faq-ucc21710-q1-schematic-and-layout-recommendation

Did you check it, do you have any specific question?