TPS40304: TPS40304

The Excel tool or the WEBENCH ® Design can not work well according to the practice.

Is there a way for debuging？

For examp, I measure some wave，and then change some values through calculation according to the wave .

li baokang li baokang 

It would have been much more helpful if you had attached the Excel file to the message rather than screen-shots, but:

Neither of your excel files have a quantity for the number of output capacitors, and the first one shows a capacitance of 200μF with 100,000mΩ (100Ω) ESR.  Without the correct inputs, the tools are not going to generate the correct outputs.

Your WeBench design is based on 1x 100μF output capacitor, which does not appear to be correct according to your schematic either.

From your schematic, their are 2x 100μF + 6x 22μF

From the datasheets you shared, the 22μF has an ESR of about 3mΩ and the 100μF has an ESR of about 2.5mΩ 

When I enter those values for Cout into the Excel tool, along with the target crossover frequency of 95kHz, I see these results

But 2 things in this concern me. 

First, the phase in the total System Bode (Right Graph) is VERY low just above 10kHz.  There isn't enough phase boost at the LC resonance due to the low DCR of the inductor and ESR of the output capacitors. (Note:  the DCR in the images you shared is 0.2mΩ or 200μΩ, which I'm not sure is correct, but without the details from the inductor, I don't have another value to use)

Second, the Error Amplifier Bode (middle graph) is being clamped by the Open Loop Gain-Bandwidth product of the Error Amplifier, not the R-C compensation components and the Vout to COMP gain is very high at the 600kHz switching frequency, between 23 and 24 dB, which can produce a very high ripple voltage at the Ramp comparator.

First, I'm going to walk you through using the "Manually Enter P's and Z's" which is for Poles and Zeros.  To do that, we need to make sure the "Manually Enter R's and C's (Cell K4) is selected as "No" and Manually Enter P's and Z's (Cell K13) is "Yes"   (without frequencies entered, this will generate a lot of #Div/0! errors, but as we enter poles and zeroes, they will clear up.

Since the L-C resonance is 8.735kHz (Cell N4) we'll place the two poles around 8.7kHz at 5,000Hz and 10,000Hz (the entries are in Hz in cells J14 and J15)  For the Poles, we'll place the first one at the target crossover of 95kHz and the second at half of the switching frequency at 300khz 

That addresses both of the problems, but the phase margin is low at only 21 degrees 

Reducing the target loop bandwidth to 60kHz and pushing the first pole frequency up to 150,000Hz we get the phase margin up to 43 degrees

Here is the excel tool with these settings - Copy of TPS40K TPS5 Type III Loop Stability kVenable_pole_zero.xlsm 

It's also possible to use the "Manually enter R's & C's but this requires more detailed understanding of how the Rs and Cs set the pole and zero frequencies.

The primary integrator of the control loop, which gives it high DC gain and good regulation accuracy is set by R1 and C2

The two zeros come from R1 & C1 and R3 & C2.

Doubling C1 from 1000pF to 2200pF will reduce the frequency of the first zero by half, but it also doubles the resulting gain.  To counter that we'll double C2 from 330pF to 680pF and cut R3 in half from 33,000Ω to 15,000Ω.

To further boost the phase at resonance, we'll reduce second zero by half, but doubling C2 again from 680pF to 1200pF.

This has boosted the phase at 10kHz close to 45 degrees, but the gain is still very high at the switching frequency, and the Error Amplifier Bode is still up against the Open Loop Gain-Bandwidth product of the Amplifier.

To lower the pole frequencies, increase R2 and C3.  They are currently at 264kHz and 1.3MHz respectively

Increasing R2 to 511Ω and C3 to 33pF moves those poles to 141kHz and 330kHz respectively, which provides good margin between the closed loop error amplifier gain in dark blue and the open loop gain-bandwidth limit in red of the middle graph, but leaves the phase margin low at 31 degrees in cell J20.

To lower than gain and improve the phase, we'll increase C2 from 1200pF to 1500pF and reduce R3 from 15,000Ω and R2 from 511Ω to 402Ω.

This provides 74kHz of bandwidth, 44.9 degrees of phase margin, some margin between the closed and open loop gain of the error amplifier and good phase margin at the LC resonance.

Here is that version of the excel file - Copy of TPS40K TPS5 Type III Loop Stability kVenable_Rs_Cs.xlsm

As for a debug process, if you have access to a network analyzer, you can swamp out the loop by placing a large C2 capacitor to create a single dominant pole loop and use the network analyzer to measure the loop response from COMP to VOUT to measure the open loop response of the PWM modulator and L-C filter and then design an R-C compensation network to match that filter.

First, determine the gain of the PWM + LC filter at the desired crossover frequency, it will generally be negative.  Your Network will need a positive version of that gain at that same frequency.  With all ceramic output capacitors whose ESR zero frequencies are above the crossover frequency, that gain will be set by C1 into R2 with R2 / (1/2*pi*C2*f) equal to the necessary gain factor.  (F is the target crossover frequency)

Second, determine the L-C resonance from the frequency plot.  Place the R1 / C1 and R2 / C2 zeros at or closely around the L-C resonance to provide enough phase boost at the L-C resonance.

Finally, size R3 and C3 to provide roll off poles before the switching frequency.  For an all ceramic output filter like this, we generally place them about 1/4 and 1/2 the switching frequency to ensure enough gain reduction at the switching frequency.

Hopefully all of this helps, and provides confidence in the Excel and WeBench tools when they are provided the proper inputs.