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CSD25480F3: Pulsed Drain Current and Vds Rating Question

Part Number: CSD25480F3

Tool/software:

Hello,

The CSD25480F3 is speced to handle -10.6 [A] of pulsed drain current. A "pulse" is defined as ≤100 μs, duty cycle ≤1%. I am using the Unencrypted Pspice model of the CSD25480F3 in a fast switching circuit, and the CSD25480F3 is providing pulsed drain currents of -3.3 [A] that last 3.3 [ns] in duration and have a 20% duty cycle. Given the above definition of a pulse, will this MOSFET be able to handle these current pulses? 

Along with the above question, I am also biasing the CSD25480F3 at exactly Vds = -20 [V]. Given that -20 [V] is the absolute maximum rating of the device, will the CSD25480F3 be able to reliably withstand this voltage?

Thank you!

Braden

  • Hello Braden,

    Thanks for your interest in TI FETs. The pulsed drain current in the FET datasheet is calculated as shown in the blog at the link below. I think a 3.3ns pulse width is going to be difficult to achieve with this FET. The turn-on/turn-off delay times as well as the rise and fall time specified in the datasheet already exceed 3ns. Is the FET switching at some frequency and duty cycle or is this a single shot pulse? Can you share your simulation and results? No, TI does not recommend operating the FET with Vds = BVDSS. Any transients, overshoot or voltage regulation could push the FET into avalanche which can damage or destroy the FET. Normally, customers derate the maximum operating voltage to 80% or 90% of BVDSS. Please let me know what I can do to further assist you.

    https://www.ti.com/lit/ta/ssztcp0/ssztcp0.pdf

    Thanks,

    John Wallace

    TI FET Applications

  • Hi John,

    Thank you for your reply! Please see my private message for more details on this design.

    Cheers,

    Braden