LM63635EVM: In heavy load performance condition, voltage on SW pin drops obviously on the rising edge

Hello Andrew,

That's how I make the test. The oscilloscope and the probe support 1GHz bandwidth, with which I believe measurement error doesn't count. 

Here are my tests and guess:

1. Connect a resistor in series and observe the voltage drop：

Cboot=220nF, R=0ohm vs Cboot=220nF, R=10ohm

More drops happen when R=10ohm 

2. Enlarge Cboot and observe the voltage drop：

Cboot=330nF vs Cboot=470nF (R=0ohm)

The drop is  suppressed

3. I think during the rising edge, the charge of Cboot is consumed too much, and thus the charging MOS is opened, as shown in below:

The voltage on BST never drops below 12V, since the 12V Vin sustains it through D1. 

Besides, when load is weak, 1A for example, the voltage drop（when Cboot=220nF） behaves just like when Cboot=470nF， which might confirms my guess?

Please help confirm my guess, thanks

Hi,

I was busy and unable to answer this thread today. I apologize for the delayed response.

Thanks,

Andrew

Hi，

Thanks for response, I'll just wait. The problem is not urgent, but it's meaningful to clear the fog.

Thanks,

Junjie

Hi,

I was busy with an urgent customer issue and unable to answer this thread today. I apologize for the delayed response.

Thanks,

Andrew

Hi，

Excuse me, I wonder is there any progress on this thread. 

Thanks,

Junjie 

Hi Junjie,

I checked with no load on the EVM and didn't see that. I will check again tomorrow.

Thanks,
Andrew

Hi Andrew,

The rising edge non-monotonicity I described occurs with heavy load only. Besides, heavier load, worse situation

Thanks,

Junjie

Hi Junjie,

I observed the same thing on the bench. It's not as pronounced as your first photo but the effect is still present. I'm checking with the designer, but I'm pretty sure this is expected behavior.

Thanks,
Andrew

Hi Andrew,

Thanks for your replies

Junjie

Hi Andrew,

We connect a 10pF capacitor in parallel between 12VIN and SW to suppress the vibration. 

But results show that the cap make the vibration even a bit worse， which might suggest that the high-side NMOS driver shut abnormally.

May I ask if you could test the performance of the level shifter and the high-side NMOS driver？We believe that SW’s raise should have a bad influence on them