TPS7A57: TIDA-050061 Reference Design

I'd like to update my original information. I think 13.5A is sufficient. I realize that is the actual max output current of the TIDA-050061 reference design. So I'd be trying to take scale this to 27A.

Hi Matt,

Please reply back with any additional questions you may have.  Here are the answers to your first questions:

1. Yes, this is completely fine.  We have customers that parallel up to 10 LDO's without issue.  I'm aware of multiple parallel designs using the TPS7A57 where at least 20A is being achieved without any issues.

2. Yes, similar performance is expected. Your top priority is to focus on the layout as the PCB impedance will combine with the small Rb and impact the current sharing (we show this in our new white papers, copied below).  I can help review your layout or offer suggestions.  You can also send me your schematic for review prior to going into placement / route if you want.  We routinely review schematics, including parallel LDO's, so this is no problem.

3. You can try this approach.  I did something just like this with EVM's when I wrote up the new white papers (copied below), however in my case the ballast resistor values were larger because the LDO I used was older than the TPS7A57.  The TPS7A57 is state of the art so the ballast resistor values are small.  Thus the issue you may encounter is the connection of the two designs is not trivial since the ballast resistance is just 3-4 miliohms (including PCB copper impedance).  Even with large AWG wire you may see statistically significant impedance in the wiring which will affect the current sharing. I suspect the LDO's on one PCB will have current sharing grouped together and the LDO's on the other PCB will have current sharing grouped together, but the two PCB's will not current share as well as they would if the LDO's were on the same PCB.  Thankfully we have demonstrated in the new white papers (copied below) that we can exactly predict the current sharing if we know the PCB impedance and ballast resistance.  Thus you just need a post layout simulation to help guide you.

Let me know if you can tell me what is being powered in this design. That information helps us tailor future reference designs to our customers needs.

Resources that I recommend you use:

#1: The MS Excel calculator (there is no VBA, it's just MS excel equations): https://www.ti.com/tool/PARALLEL-LDO-CALC

(Alternatively you can give me your system requirements and I can fill out the excel file for you, and screen shot the results here if that is easier for you)

#2-3: The new white papers:

https://www.ti.com/lit/wp/sbva100/sbva100.pdf

https://www.ti.com/lit/wp/sbva093/sbva093.pdf

Thanks,

Stephen

Hi Stephen,

Thank you so much for your response.

I have some reading/work to do to make sure I am fully ready to implement this design.

We are powering a phased array antenna system (satellite communications). 

Based on your response to 3. I think it might make the most sense to begin the design and possibly try the EVM method out as well, since it is relatively cheap, and I think would provide a learning opportunity in the meantime. 

4. Do you have any recommendations on the best way to simulate the PCB impedance post layout/route?

For a little context on my experience with this type of analysis:

*I have access to SI/PI tools from Keysight but, I'm relatively new to using them for PCB trace impedance verification. 

*I've used the Altium PDN tools but only for voltage drop and current density analysis. I tried to extrapolate a voltage drop on a power plane of this much at this current means a bulk impedance on that copper of Vdrop/Iload = PCB trace impedance, but this seemed pretty handwavy to me.

Once again thank you so much for your help, I am super appreciative. 

Thanks, Matt

Hi Matt,

We can move this to email if you would prefer.  Some additional thoughts:

1. We can take measurements here in our lab to supplement your work.  I'm confident that 27A will be fine with this LDO.

2. For post route simulation, you need something that can do DC resistance.  The voltage drop analysis works: you just set up the load to be 1A and find the voltage drop, which is the DC resistance using ohms law.  Per the white papers, you will want to do this at cold and hot temperatures (don't forget the temp rise of the copper, which may be at least a few degrees C for a power plane with 27A).  This is just a power integrity analysis and 95% of the work is in the initial setup.  Altium is not the best choice for your work because Altium cannot make sense of components, which may add significant metal in real designs.  (Of course, if there are no significant components between the LDO's and the load then perhaps Altium would work fine).  Better options are the higher end software. 

Is your 27A going to the antenna port itself, or some FPGA's / ADC's / something else? Again, I understand if you cannot say, but let me know if you can as it does help us with future reference design work.

Thanks,

Stephen

Hi Stephen, 

Email is good: matt@utvate.com

1. That would be amazing if you could.

2. The only components would be the ballast resistor and bypass capacitors then the RFICs which are a BGA component.  Leading into your final question, the 27 A goes directly to beamforming ICs. So basically, it's powering RF Amplifiers in a BGA package. Generally beamforming ICs are RF amplifiers with some digital control circuitry and phase shifters, where the majority of the power draw is the RF amplifiers within the beamformer ICs. We use a lot of these RFICs which then split/combine the RF to/from the antenna port.