Tool/software:
Hi Team,
Our customer would like to request for the Rth vs copper area graph for LP2951-50QDRGRQ1. Do we have this information?
Regards,
Danilo
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Tool/software:
Hi Team,
Our customer would like to request for the Rth vs copper area graph for LP2951-50QDRGRQ1. Do we have this information?
Regards,
Danilo
Hi Danilo,
I'm going to submit a request to the thermal modeling team to generate this plot for us since it is not currently available for this device. Expect a turnaround in 4-5 weeks since they are a bit occupied right now. Meanwhile, please confirm the modeling specs below so I can put the request in early.
T_a = 25 DegC
Directions: Use the JEDEC High-K layout with 2nd and 3rd layer pours which dont vary and their areas equal the full board size. Vary the top and bottom layer Cu pours together. Measure R_Theta_JA vs area of top and bottom layers. Via size =10 mil with 10 mil annular ring. Number of vias = 4