• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 2 answers
  • Subscribers 63 subscribers
  • Views 397 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS746-Q1: Start-up with 40uF output capacitance

Robin D
Prodigy 20 points
Part Number: TPS746-Q1
Other Parts Discussed in Thread: LP3990,

Tool/software:

Hi,

I'm looking to use the fixed 3.3V version of this part (TPS74633PQWDRVRQ1) in a design.  Vin = 5 - 6V.  The load on the output will only be ~15mA, but there's ~40uF of capacitance on the rail provided by this LDO (from various decoupling caps on the board, probably more like 10uF after derating, as they're small 0402 parts).

My question is whether this part will happily start-up with 40uF of capacitance on its output, given the corresponding inrush current at switch-on?  Will the devices 'foldback current limit' and 'thermal protection' just cycle a few times while the output caps charge up, before finally settling and maintain the load?

Thanks,

Robin

  • 0
    TI__Expert 4600 points

    Hi Robin,

    The output capacitor value of 40uF falls within the range of recommended operating condition of the device.

    However, the input cap value needs to be comparable with the output cap such that the current drawn in startup won't trigger the short circuit current limit circuit.

    Robin D said:
    whether this part will happily start-up with 40uF of capacitance on its output,

    If Cin is comparable to Cout, then there shouldn't be an issue at startup.

    Regards,

    Bobby

  • 0 in reply to Bobby
    Prodigy 20 points

    Thanks Bobby,

    Is it a problem if the device relies on the short circuit protection to limit the current while the decoupling capacitors on the 3.3V domain charge up from 0V?

    Unfortunately I don't have room on the board for large input caps.

    Thanks,

    Robin

  • 0 in reply to Robin D
    TI__Expert 4600 points

    Hi Robin,

    What is your Cin?

  • 0 in reply to Bobby
    Prodigy 20 points

    I've attached my schematic.  I hadn't been considering the cap derating, so the total output capacitance is more like 16uF, rather than 40uF.

    I managed to fit more inputs caps on, looks extreme but the derated values are only:

    Cin=13.6uF derated (5V bias).

    Cout=15.9uF derated (3.3V bias)

    22uF/10VDC caps are Murata GRM158R61A226ME15D.

    10uF/10VDC caps are Murata GRT155R61A106ME13D.

    Derated values are taken from Murata's SimSurfing tool.

    The load will draw max 15mA (with the exception of start-up/inrush).

    I tried to find a Spice model to simulate the circuit at turn-on, but it appears that one isn't available?

    Thanks,

    Robin

  • 0 in reply to Robin D
    TI__Expert 4600 points

    Hi Robin,

    Derated values are the values that matter.

    But are you sure you have the right schematic? From the one that you have attached, the nominal value of Vin is 4*22= 88uF, and for Cout=10uF, as opposite to what you described initially.

    Robin D said:

    Cin=13.6uF derated (5V bias).

    Cout=15.9uF derated (3.3V bias)

    From this information, Cin is comparable to Cout, and you will not have current limit issues during startup.

    Regards,

    Bobby

  • 0 in reply to Bobby
    Prodigy 20 points

    Thanks Bobby, the derated cap values are shown in pink - 4x 22uF caps end up being 4x 2.7uF after derating.  The output shows one 10uF, the others are decoupling various other ICs on the PCB and so aren't shown. The effective output capacitance is shown in the pink text, however.

    It sounds like we shouldn't have any problems with this circuit, thanks again for your help Bobby!

  • 0 in reply to Bobby
    Prodigy 20 points

    Hi Bobby, the capacitors I'm using are rated 22uF each, I kept that value on the schematic as I was trying to simulate the current surge from the VDD_5V0 supply when the input power is initially switched on.  As the input power ramps up from 0V, I guess the caps will act like 88uF of total capacitance, but as the voltage increases to 5V, it will (eventually) look like ~13uF.

    The initial powering up of the VDD_5V supply is a concern for me, as the 88uF of capacitance will create a sizeable current surge.  Simulations (using the LP3990, as I couldn't get a spice model for the TPS746-Q1) suggest ~6A surge.  I've added 0603 pads on the VDD_5V0 input line, to allow me to add a small resistor in series with the supply - a 10R resistor looks to lower the surge to ~600mA.  The circuit will draw such little current in operation, that the 10R resistor should have negligible effect.

    I looked at using a non-linear model for the caps to simulate the voltage derating, with either a piecewise or Tanh function, but things quickly escalated out with my knowledge!

    I suspect I'm overthinking this design somewhat.  I'll play around with different input cap values and see what works. a single 10uF/10 VDC input may well prove sufficient.