• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 65 subscribers
  • Views 169 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC14341-Q1: .

Yadala Tejasri
Prodigy 60 points
Part Number: UCC14341-Q1

Tool/software:

Hello Team,

I am working on UCC14341-Q1 IC. I want to understand more detail on UVLO. At same conditions, IC is going to auto recovery and sometimes to latch-off mode.

. Protection mode, auto-recovery. In this mode, the module is off, due to the input UVLO or OVLO protection. After the input voltage fault is cleared, depending on the ENA pin voltage condition, it either becomes disabled mode if the ENA pin voltage is low, or it goes through soft-start mode to the normal operation mode.

5. Protection mode, latched-off. In this mode, the module is off, due to other protections. The module remains off even the fault causing the protection is cleared. Recycling VVIN operation must ensure the input voltage goes below the analog UVLO falling threshold (VVIN_ ANALOG_UVLOP_FALLING ) first to reset the latch-off state, or the ENA pin is toggled Low (OFF) then High (ON).

Could you explain in detail on this.

Thank you,

Tejasri.

  • 0
    TI__Mastermind 27555 points
    1. Make sure you are using the latest version 8 UCC14341 Excel Design Tool you can download here.
      1. Be sure to implement the RLIM=RDR (resistor/diode/resistor) and COUT1b configurations highlighted in the Excel Design Tool
    2. Make sure the high frequency bypass capacitors are located directly at the IC pins
      1. For a test you can ask to solder a 0402 size, 220pF directly across VIN-GNDP and VDD-VEE. The 0402 will fit right on the IC pins/leadframe.
    3. Check the voltage rating vs applied DC bias for the output capacitors and make sure the VDD-COM and VEE-COM capacitors are placed at the gate driver and the ratio of these capacitators is as close to the ratio result coming from the Excel calculator.
    4. Your understanding of the different fault modes is correct. You can also refer to section 5.9 of the UCC4341EVM-069 User Guide to see waveforms and detailed explanation. Below is a list of all the possible shutdown methods, fault protection that can be checked:
      1. UVP(FBVDD) relative 90% of Vreg setpoint
      2. OVP(FBVDD) relative 110% of Vreg setpoint
      3. OVLO(VDD-VEE) absolute value >31V
      4. UVP(FBVEE) relative 90% of Vreg setpoint
      5. OVP(FBVEE) relative 110% of Vreg setpoint
      6. Over temperature, secondary-side, TSHUT(secondary)
      7. Over temperature, primary-side, TSHUT(primary)
      8. Soft-start timer 16ms (UCC14240), extended to 34.8ms (UCC14241 and UCC14341) – protect if shorted at power-up

    Steve

  • 0
    Prodigy 60 points

    Hello Steven,

    Design is same in both the cases.

    Vin is sensed as UVLO which is expected and EN voltage is HIGH ( 5V ).

    case 1: IC sensed as UVLO fault and went into auto recovery mode and automatically resetting.

    case 2: IC sensed as UVLO fault and went into latch mode and not resetting.

    So, could you explain the difference between auto recovery and latch mode. Considering which one, IC is choosing the mode.

    bcoz it’s not clear in the data sheet.

    Thank you,

    Tejasri.

  • 0 in reply to Yadala Tejasri
    TI__Mastermind 27555 points

    Input voltage UVLO is auto recover event, once the input voltage returns to the valid range. Output UVLO is latching and can be reset by toggling EN or input voltage. You can have an input UVLO event that may not trigger an output UVLO and in this case you would see auto recovery. On the other hand, you could have an input UVLO event that also results in an output UVLO event and in this case, when the input recovers, the output remains latched off. To discern between the two, you can use your 4-channel scope to monitor VIN, FBVDD, FBVEE and PG signals while you introduce the fault conditions for the two cases you mentioned.

    Regards,

    Steve

  • 0 in reply to Steven Mappus1
    Prodigy 60 points

    Hello Steve,

    I understood now both the scenarios.

    As you suggested, I already probed and confirming that both the cases are happening similar as you explained.

    case 1: only input UVLO and auto rcovery is happening

    Case 2: both input and output UVLO and going to latch.

    My question here is, in both the cases design is same.

    what is the reason for happening of different modes for same value of input UVLO

    why for same condition, IC reacting as different?

    Thank you,

    Tejasri.

  • 0 in reply to Yadala Tejasri
    Prodigy 60 points

    I am attaching the waveforms for reference:

    Case 1:

    Yellow- Vin

    Blue - Ufbvdd

    Red - Ufbvee

    Case 2:

    Red - Vin

    Green - secondary VDD

    pink - FBVEE

    Dark green - FBVDD

    Thank you.

  • 0 in reply to Yadala Tejasri
    Prodigy 60 points

    In both the cases, input UVLO event results in an output UVLO event.

    but case 1: auto recovery is happening

    case2: latching is happening.

  • 0 in reply to Yadala Tejasri
    TI__Mastermind 27555 points

    I guess I don't see the relationship between the two waveforms? Mu understanding was that both ICs are operating under the exact same electrical conditions and IC1 enters "case 1" but IC 2 enters "case 2" protection? The two waveforms you are showing do not seem to be the same conditions? 

    In any case, it could be that the load seen by the UCC14341 is slightly different in each case? A simple way to debug would be to swap the two ICs and see if the issue moves with the IC? It could be that the case 1 board is marginally close to entering case 2 and vice versa? 

    My recommendations:

    1. Do what you can to make sure the input voltage does not have such a large negative dip.
      1. Reduce impedance between the VIN source (pre-regulator) and VINP pins of UCC14341
      2. Make sure the pre-regulator has enough output capacitance 
      3. Make sure the pre-regulator is not reaching current limit, especially during start up when inrush current is high.
    2. Make sure the gate driver capacitors are located directly at the gate driver IC pins
    3. Make sure the VDD-VEE UCC14341 capacitors are located directly at the UCC14341 pins
    4. The RLIM function does its best to compensate for charge imbalance that might exist between VDD-COM and VEE-COM.
      1. Make sure you are using the RLIM set up in the RDR configuration as detailed in the UCC14341 Excel Design Tool.
      2. It could be that the load seen in case 1 vs case 2 is slightly different and this can cause an imbalance the RLIM may not be able to compensate for?
      3. Check you capacitance ratio and make sure it is correct according to the Excel Design Tool calculations
      4. Check capacitor values, considering DC bias effect, temp and tolerance variation.

    Regard,

    Steve