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TPS6594-Q1: Configuration of PMIC on SK-AM69

Marek Kvas
Prodigy 51 points
Part Number: TPS6594-Q1
Other Parts Discussed in Thread: SK-AM69, , AM69

Tool/software:

Dear TI,

we have SK-AM69 board that uses PMIC from family TPS6594x-q1. We are trying to understand how PMIC works and whether we can use it in our design with some adjustments (e.g. we would like to use BUCK5 for other purposes and 32Khz output).

PMIC is marked as TPS6594133ARWERQ1 in the board schematic. Package marking of the PMIC on the board is PTPS659x. Can we expect that PMIC on the board has the same programing as chips that we can buy now under part number TPS6594133ARWERQ1?

Can you provide us with json configuration files readable by Scalable PMIC GUI tool for both these chips, so we can understand programing in detail?

When we read back binary NVM configuration from the board is it possible to "decompile it" to GUI configuration file so it can be inspected in GUI (including state machines)?

I found only two documents describing the chip - general TPS6594-Q1 Power Management IC (PMIC) for Processors with 5 Bucks and 4 LDOs datasheet (Rev. B) and one specifically for the part number Powering Jacinto 7 SoC For Isolated Power Groups With TPS6594133A-Q1 + Dual HCPS.

The second one describes a lot of details, but it seems to me not to agree with starter kit schematics. E.g. the document says that GPIO8 switches between isolated and non-isolated PDN scheme, but starter kit schematic says it controls watchdog enable (and provides 32kHz output). The description of GPIO8 fits more GPIO10 on the kit. The document provides two PDN diagrams 3A and 3F - both do use BUCK5 convertor, but starter kit doesn't use it. What PDN is really used on starter kit? Can you help me understand the differences between the document and starter kit functions?

There are plenty of references to PDN-XY. Is there any document describing logic of the marking or table of features of each PDN?

Thanks for information

Marek

  • 0
    TI__Genius 17983 points

    Hello Marek,

    Marek Kvas said:

    we have SK-AM69 board that uses PMIC from family TPS6594x-q1. We are trying to understand how PMIC works and whether we can use it in our design with some adjustments (e.g. we would like to use BUCK5 for other purposes and 32Khz output).

    PMIC is marked as TPS6594133ARWERQ1 in the board schematic. Package marking of the PMIC on the board is PTPS659x. Can we expect that PMIC on the board has the same programing as chips that we can buy now under part number TPS6594133ARWERQ1?

    That is correct.

    Marek Kvas said:

    Can you provide us with json configuration files readable by Scalable PMIC GUI tool for both these chips, so we can understand programing in detail?

    The .json files no longer are available for the current revision of the TPS6594133A.

    Marek Kvas said:

    When we read back binary NVM configuration from the board is it possible to "decompile it" to GUI configuration file so it can be inspected in GUI (including state machines)?

    Unfortunately, there's no decompile options available for the binaries of the TPS6594.

    Marek Kvas said:

    I found only two documents describing the chip - general TPS6594-Q1 Power Management IC (PMIC) for Processors with 5 Bucks and 4 LDOs datasheet (Rev. B) and one specifically for the part number Powering Jacinto 7 SoC For Isolated Power Groups With TPS6594133A-Q1 + Dual HCPS.

    The second one describes a lot of details, but it seems to me not to agree with starter kit schematics. E.g. the document says that GPIO8 switches between isolated and non-isolated PDN scheme, but starter kit schematic says it controls watchdog enable (and provides 32kHz output). The description of GPIO8 fits more GPIO10 on the kit. The document provides two PDN diagrams 3A and 3F - both do use BUCK5 convertor, but starter kit doesn't use it. What PDN is really used on starter kit? Can you help me understand the differences between the document and starter kit functions?

    There are plenty of references to PDN-XY. Is there any document describing logic of the marking or table of features of each PDN?

    Looking if we have a comprehensive document describing the logic behind the PDN-XY. In short PDN-3X, where X represents modifications to the PDN-3A to PDN-3F are modifications that have less hardware features to F which contains the minimal set amount of features, PDN-3G to PDN-3M have the combined grouping. A-F isolated grouping and G-M combined grouping. The User's guide describes both, but only has images for A & F.

    GPIO8 is used as a WD disable, but it only functions as such during the start up period with it sampled, then changes to the MAIN_PWR_IRQ pin in ACTIVE state. So to meet requirements, GPIO8 can not be change to suit any other functionality, nor can GPIO10.

    BUCK5 can be enabled as a separate power resources, but will need to have it's assignment through I2C writes.

    I'll try to get the information on the starter kit, but can you give the board number or part number for the starter kit to make sure what PDN is used on the device.

    Best Regards,

    Nicholas McNamara

  • 0 in reply to Nicholas McNamara
    Prodigy 51 points

    Hello Nicholas,

    thanks for your answer. I apologize for my delay answer, I was out of office. Please let me continue our discussion.

    1) PMIC fw version

    Marek Kvas said:

    we have SK-AM69 board that uses PMIC from family TPS6594x-q1. We are trying to understand how PMIC works and whether we can use it in our design with some adjustments (e.g. we would like to use BUCK5 for other purposes and 32Khz output).

    PMIC is marked as TPS6594133ARWERQ1 in the board schematic. Package marking of the PMIC on the board is PTPS659x. Can we expect that PMIC on the board has the same programing as chips that we can buy now under part number TPS6594133ARWERQ1?

    Nicholas McNamara said:

    That is correct.

    I found this thread providing binary configuration of NVM. I compared it with NVM read out of our board and they are very different. The linked thread mentions change in watchdog behavior and PCN announcing it. Can I somehow find all related PCN or change log or similar document?
    2) JSON
    Marek Kvas said:

    Can you provide us with json configuration files readable by Scalable PMIC GUI tool for both these chips, so we can understand programing in detail?

    Nicholas McNamara said:

    The .json files no longer are available for the current revision of the TPS6594133A.

    Ok.

    3) Readback NVM decompilation
    Marek Kvas said:
    When we read back binary NVM configuration from the board is it possible to "decompile it" to GUI configuration file so it can be inspected in GUI (including state machines)
    Nicholas McNamara said:
    Unfortunately, there's no decompile options available for the binaries of the TPS6594.
    Ok.

    4) Starter kit PDN documentation

    Marek Kvas said:

    I found only two documents describing the chip - general TPS6594-Q1 Power Management IC (PMIC) for Processors with 5 Bucks and 4 LDOs datasheet (Rev. B) and one specifically for the part number Powering Jacinto 7 SoC For Isolated Power Groups With TPS6594133A-Q1 + Dual HCPS.

    The second one describes a lot of details, but it seems to me not to agree with starter kit schematics. E.g. the document says that GPIO8 switches between isolated and non-isolated PDN scheme, but starter kit schematic says it controls watchdog enable (and provides 32kHz output). The description of GPIO8 fits more GPIO10 on the kit. The document provides two PDN diagrams 3A and 3F - both do use BUCK5 convertor, but starter kit doesn't use it. What PDN is really used on starter kit? Can you help me understand the differences between the document and starter kit functions?

    There are plenty of references to PDN-XY. Is there any document describing logic of the marking or table of features of each PDN?

    Nicholas McNamara said:

    Looking if we have a comprehensive document describing the logic behind the PDN-XY. In short PDN-3X, where X represents modifications to the PDN-3A to PDN-3F are modifications that have less hardware features to F which contains the minimal set amount of features, PDN-3G to PDN-3M have the combined grouping. A-F isolated grouping and G-M combined grouping. The User's guide describes both, but only has images for A & F.

    Thanks for overview. Can you please refer me to chapter describing non-isolated case for discussed part number? I really cannot find anything more than chapter 2.2 Control mapping, second paragraph - describing switching using GPIO8.

    Nicholas McNamara said:

    GPIO8 is used as a WD disable, but it only functions as such during the start up period with it sampled, then changes to the MAIN_PWR_IRQ pin in ACTIVE state. So to meet requirements, GPIO8 can not be change to suit any other functionality, nor can GPIO10.

    Chapter 2.2 Control mapping, second paragraph says:"In this PDN, GPIO8 has been designed to provide run-time PDN configuration resulting in a flexible PMIC that adapts to each board design. A logic low input at the beginning of the power up sequence commands the PMIC to support isolated MCU and Main power groups which includes BUCK5 in the power up sequence.". Is that User's guide statement in agreement with your explanation?

    Nicholas McNamara said:

    BUCK5 can be enabled as a separate power resources, but will need to have it's assignment through I2C writes.

    It means SW must enable it after each power cycle, right?

    Nicholas McNamara said:

    I'll try to get the information on the starter kit, but can you give the board number or part number for the starter kit to make sure what PDN is used on the device.

    That would be great. Board marking says AM69 PROCESSOR STARTER KIT PCB# PROC154E3.

    Thanks for information

    Best regards

    Marek

  • +1 in reply to Marek Kvas
    TI__Genius 17983 points

    Hello Marek,

    Marek Kvas said:
    I found this thread providing binary configuration of NVM. I compared it with NVM read out of our board and they are very different. The linked thread mentions change in watchdog behavior and PCN announcing it. Can I somehow find all related PCN or change log or similar document?

    I would assume that the one on the SDK is older therefor would not complete the check on the register mapping.

    Here's a link to the PCN: (click me here)

    Marek Kvas said:
    Thanks for overview. Can you please refer me to chapter describing non-isolated case for discussed part number? I really cannot find anything more than chapter 2.2 Control mapping, second paragraph - describing switching using GPIO8.

    That would be the only section that describes this, the non-isolated case, we are working on a new guide to include these, the finalized version is near future.

    Marek Kvas said:
    Chapter 2.2 Control mapping, second paragraph says:"In this PDN, GPIO8 has been designed to provide run-time PDN configuration resulting in a flexible PMIC that adapts to each board design. A logic low input at the beginning of the power up sequence commands the PMIC to support isolated MCU and Main power groups which includes BUCK5 in the power up sequence.". Is that User's guide statement in agreement with your explanation?

    It is not, in my statement I have mistakenly said GPIO8 is a WD PIN, this is incorrect, it functions exactly as the User's Manual says.

    GPIO9 works initially as a watchdog disable pin (on Rev5) then turns into the EN_VIO_3V3 output, this is for debugging purposes when the WD is interfering in development.

    From PROC141E3

    Marek Kvas said:

    It means SW must enable it after each power cycle, right?

    That's correct, in the event of a logical high on GPIO8 at the beginning of the power up sequence that would cause the part to become non-isolated grouping of power resources.

    Marek Kvas said:
    That would be great. Board marking says AM69 PROCESSOR STARTER KIT PCB# PROC154E3.

    Thank you for providing the EVM for the AM69, I was able to find the device files, unfortunately it does not say what revision of the TPS6594133A was used with this build. Regardless, the devices bought from TI will be revision 5.

    Best Regards,

    Nicholas

  • 0 in reply to Nicholas McNamara
    Prodigy 51 points

    Hello Nicholas,

    thanks for your answers. I consider TPS6594 PMIC great part, but we are not ready to use it. Maybe with future documentation and PMIC GUI version we will change our mind.

    Best regards

    Marek