Hi
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Hi Tommy,
Thanks for reaching out. Please find the below layout check list which may help. Let me know if you have any further questions.
Best regards,
Diang
Hi Diang,
got it, thanks for you data, but we want to you can help us double confirm this schematic whether any problem and if layout can also check, thanks.
.zip file password:DCs1163y67PR
Hi Tommy,
Sure, we can help to check the schematic and layout. Should be able to get back to you by the end of next week.
By the way, the brd. file password is incorrect.

Best regards,
Diang
Hi Tommy,
Thanks for your reply. I checked your new password but it is still incorrect...
Could you double check again?
Best regards,
Diang
Hi Aaron,
The password works now. Will get back to you by this week. Thanks!
Best regards,
Diang
Hi Aaron and Tommy,
Thanks for your patience. Please see the comments below:
1. The typical Ethernet PHY does not need thick wire but considering the PoE is for higher current than data, it is recommended to use a thicker wire at Ethernet port.

2. The primary side FET gate loop is important

3. Though in many cases there is no need to mount the snubber circuit at primary side when you have the RCD clamping, but it is recommended to have a 0805 or larger size snubber resistor.

4. The PSR wire is long, which may influence the Vout regulation accuracy.

Best regards,
Diang
Hi Aaron,
Thanks for your reply.
I will close this thread for now. Please reply or open a new thread if you have further questions.
Best regards,
Diang