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LM25149-Q1: CNFG pin mis sample

Shinji Tsuji
Genius 12898 points
Part Number: LM25149-Q1
Other Parts Discussed in Thread: LM25149

Tool/software:

Hi team,

I am planning to use LM25149-Q1 in dual phase and connect 71.5kohm on primary IC and 90.9kohm on secondary IC.

As an automotive risk analysis, I am considering if resistors connected to CNFG pin get weak short by condensation which result to unexpected configuration. 

Could you please advise if impedance of resistors connected to CNFG pin becomes lower than expected as below matrix?

And could you also advise the possible way to detect and recover from that condition?

regards,

  • 0
    TI__Genius 12475 points

    Hi,

    Thank you for your question. Are you asking what happens if the resistor connected to CNFG is shorted to GND? If this occurs, active EMI filtering will be disabled, but the output voltage will remain unaffected. Please see table 4-2 of the Pin FMA for more details.

    Please note that once VCC is above 3.3 V typical, the CNFG pin is monitored and latched, and will not allow for the configuration to be changed on the fly. Please see section 8.3.16 in the datasheet for more details on this process. 

    Thank you,

    Joshua Austria

  • 0 in reply to Joshua Austria
    TI__Genius 12898 points

    Hi Joshua-san,

    I am asking if resistance of resistors connected to CNFG pin dropped due to condensation before start up. 

    It is not hard short to GND. So I would like to know how the devices behave when resistance combination get above tables

    at start up. It is helpful if you can fill in the table above. 

    regards,

  • 0 in reply to Shinji Tsuji
    TI__Genius 12475 points

    Hi Shinji,

    When the resistor is out of range for the LM25149, it will configure for one of the option modes that are nearby the resistance value. However, TI does not guarantee performance outside of the datasheet parameters, so there may be variation as to which configuration the device will opt to during startup if the resistors are out of range as listed within the datasheet EC table (Section 7.5). 

    Thank you, 

    Joshua Austria

  • 0 in reply to Joshua Austria
    TI__Genius 12898 points

    Hi Joshua-san,

    Thank you. It helps to know the potential device status at condensation condition. 

    The next question is how does the device behaves if the hardware configures dual phase configuration, but strap option unintentionally 

    selected like both device configured as primary?

    regards,

  • 0 in reply to Shinji Tsuji
    TI__Genius 12475 points

    Hi Shinji,

    This depends. Are the devices connected? If so, please share a diagram as to how they are in your application. Additionally, would the devices be hypothetically starting up with the unintentional configuration or are they already operating as primary/secondary and then the resistance is changed?

    In any case, it can be helpful to look at the Pin FMA  to note what risks may be associated given your hypothetical conditions.

    Thank you,

    Joshua Austria

  • 0 in reply to Joshua Austria
    TI__Genius 12898 points

    Hi Joshua-san,

    The devices are connected ( I can share the diagram off-line). Can I move this to internal e2e?

    The devices are starting up unintentional configuration. (not already operating as primary, secondary) 

    regards,

  • 0 in reply to Shinji Tsuji
    TI__Genius 12475 points

    Hi Shinji,

    Yes, you can move this thread to internal E2E. I can close this thread and we can continue from there.

    Thank you,

    Joshua Austria