UCC28180: Schematic diagram review

Hello Colin, 

Thank you for your interest in the UCC28180 PFC controller. 

I have several concerns about this design: 

1.  Output voltage is set for 385Vdc, but maximum input voltage is 277Vrms which has a peak of 392V.  To accommodate this input peak, I recommend to raise Vout to ~404Vdc by changing R47 to 12.4kR.  
2.  MOV Z4 (shown as 561DK14, maybe should be 561KD14?) is located on the output side of the diode bridge DB1.  That means that all surge current that is clamped by Z4 will flow through the bridge, possibly damaging it if the surge peak is high enough.  I recommend to relocate it to the AC side of the bridge. 
I also suggest to reconsider the size of this MOV.  Maybe it should be sized larger to accommodate higher possible surge energy from an AC source big enough to power 1.5kW or more.
3.  The clamp rating of Z4 is much higher than the MOSFET and cap voltage ratings.  I recommend to lower the rated voltage of Z4.
4.  The Rds(on) of Q2 and Q3 are fairly high for this power level, if full output power is required steady-state at 85Vac input.  I think these MOSFETs will have excessive conduction loss and may overheat.  I recommend to find lower Rds(on) devices and balance conduction loss with switching loss (from Coss stored energy plus output diode capacitive charge).   If output power is derated at low-line, then maybe these devices are okay, but I don't have any information about that. 
5.  Output diode D4 is a SiC diode rated for 10A average current, but the peak currents through it are high, so Vf of this diode will be high.  I suggest to investigate the conduction loss of this diode at low-line (if full power is required) and consider to maybe add another one in parallel. 
6.  Make sure that inrush limiting is effective enough to prevent damage to bypass diode D2.  This diode can sustain high peak currents on an occasional basis, but not repetitively.
7.  VSENSE filter capacitor C14 is 820pF, which sets a filtering time constant with R47 of about ~10us.  I think it should be between 5~10 times that value for better noise suppression on VSENSE.  I suggest to increase C14 to 4700pF. 
8.  Ripple current filter cap CX2 is shown as 2.2uF.  Although this value may do a great job to filter max load ripple current, it will result in an input current distortion at light load by a significant step-change.  I suggest to reduce the value of CX2 to 0.47uF, unless the PFC load will always be high.   
9.  The netname label above capacitor E2 (at far right side of schematic) is shown as +310V, but rectified 277Vac will be 392Vpk.  I suggest to rename this net to +392V to avoid possible misunderstanding about the actual peak voltage that may appear on that net. 
10.  Driving Q2 and Q3 gates with +15V will increase gate charge (and bias power) significantly, especially if larger MOSFETs are chosen (after evaluation of concern #4).  I suggest to add 1uF across C8 and C10 to provide additional local charge storage and to add 2 series resistors (one each for C8 and C10) between +15V and VDD of the gate-driver ICs. The value of these resistors is to be chosen such that they will each drop ~5V to lower Vgs max to about 10V instead of the full 15V. 
Gate-drive IN+ voltage at U2 and U3 can be higher than VDD, as long as it does not exceed the input's absolute maximum rating (20V in the case of UCC27517).
11.  It may be that AUX cap E9 can be smaller than 100uF for this PFC bias circuit.  

Regards,
Ulrich