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TPS7A26: A phenomenon in which the output voltage is not 0V when VEN=0

Part Number: TPS7A26

Tool/software:

hello. In this project, the circuit was constructed using TPS7A26.

I am trying to turn the TPS7A26 Output ON/OFF by controlling the VEN on the FPGA.

When VEN=0, Vout is output as an abnormal voltage instead of 0V. At VEN=0, VFB is 0.2V and 1.73V is output by the feedback voltage.

(@ R1= 7.5M, R2= 1M, VFB =100K) At first, it was designed with R1 = 9.1K, R2 = 1.3K, VFB = 10K (design mistake), Changed to the appropriate R1, R2, and RFB values ​​written in the datasheet.

The circuit diagram is attached below.

Please answer whether the device has been damaged or whether 0V is not output even if VEN=0.

  • Hi,

    The device is disabled and VOUT starts falling when EN voltage is below 0.4V. Does the output stay at 1.73V or is that momentarily noticed and then decays to zero? At what instance in time after disabling the device was the measurement made?

    Thank You

    Ishaan

  • VEN = 0V state, and always maintains 1.73V before VEN = H (3.3V I/O) state.

    When VEN=0, 1.73V is measured at any time.

    When VEN = 0, VFB = 0.2V is measured, and when VEN = H, VFB = 1.24V (datasheet specification).

  • The device is likely damaged. I suggest doing an ABA swap to confirm. Please let me know if that solution confirms my suspicion.

  • OK Thanks I will try it

  • I tried swap IC, But the problem isn't disappear. 

  • Did you try to change the board with the new IC?

    Please share any scopeshots which you may have taken. They will help me debug the issue. Also, please share the whole schematic if possible (including loads connected to output of the LDO) and provide any pictures of the test setup which you may have taken.

    Thank You

  • Yes. I replaced the IC and the problem is the same.
    It is impossible to upload the entire circuit for security reasons, but there is nothing special.
    The LDO's load is connected only to ADI's AD5560. However, the AD5560's power is only 1.7V (unintended problem) of TPS7A26. (Additionally, I connected a 10k load resistor to the LDO Out, but the problem is the same.)
    Instead of uploading the circuit, I will upload the Scope measurement waveform.
    The 12V power is increased, and the EN signal briefly fluctuates by 30mV before the configuration is completed, but it does not exceed VEN (High), and when VFB = 200 mV, the Out voltage is also output accordingly.

  • Could you take a clearer waveform during turn ON and turn OFF with a stronger VEN? And a picture of the assembled board with test setup showing probing locations?

    Please understand that it is a bit difficult to debug without a schematic of the LDO.

  • What's that mean "stronger VEN"? Are you talking about pull-down resistor?

    I have already provided the clear waveform for the turn-on process. I don't know why you are asking for an additional waveform.
    And I can't provide a schematic, but would it make a difference if I look at the board picture?
    The probing points are the parts in the schematic I provided at the beginning. (VEN, VFB, VOUT, VIN)
    And as I said, the only circuit related to TPS7A26 is two AD5560s and Decap (10uF x 2 + 100nF x 6) other than the attached one.
    Since there is nothing else to connect TPS7A26 other than the attached schematic, I am saying that there is no difference in looking at the entire schematic.

  • VEN (low) and VEN (High) for this device are 0.4V and 0.9V respectively. The Scopeshot you attached shows VEN_max at 27mV. So, the device should never turn ON when you would expect it to. By stronger VEN, I meant providing an enable signal that is above 0.9V.

    I want the load information to know how much load current you are pulling and whether this is in the recommended range for TPS7A26.

    The board picture would help me verify if you are using correct probing techniques. I have seen multiple instances where the probe location is very different from the parameter of interest.

    Do you have a corresponding scope measurement for the current through the LDO?