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LMR14010A: Quiescent power is high / efficiency is low

Peter Russo
Prodigy 30 points
Part Number: LMR14010A
Other Parts Discussed in Thread: LMR54410

Tool/software:

Dear TI support,
We have a number of battery-operated devices w/ LMR14010A regulators that have been running in the field for the past year or so, and we recently discovered that the batteries are not lasting as long as expected. We brought some of the devices into the lab to investigate, and found that LMR14010A power consumption is the culprit, and that swapping out the LMR14010A for a fresh one (while leaving all of the same passive components in place) brings the devices back into compliance. 
Setup notes
--Vin ~= 14.4 V, from a battery pack
--Vout = 3.3 V
--I_load is typically 1-2mA (99.9% of the time)
--I_load_max is < 50mA (the other 0.1% of the time)
--Our devices are always on, so LMR14010 runs continuously 
--Schematic:
Observations
When devices are pulled from the field: 
 -I_quiescent (LMR14010A load disconnected) = 800-1000 uA
 -Vout_no_load = 3.40 - 3.45 V -- which is outside the tolerance of the 1% feedback resistors 
 -Vfb is usually higher than spec, e.g. 0.850 V
After replacing just the LMR14010A (all of the passive components are left in place):
 -I_quiescent =~ 50-70 uA
 -Vout = 3.31 - 3.33 V -- which is within the tolerance of the 1% feedback resistors 
 -Vfb is within spec
This same behavior has been observed on multiple (~half dozen) devices tested so far. 
We're also running two side-by-side LMR14010A EVMs -- one with an old LMR14010A pulled off one of our devices, and the other with a fresh LMR14010A. All of the dev board components are stock, except for the feedback resistors (64.9k, 19.6k) to set Vout = 3.3V, and the inductor (120uH). 
EVM observations
Old LMR14010A:
No load:
 I_quiescent = 911 uA
With 50mA load applied:
 P_in = V_in * I_in = 14.37 V * 23.62 mA = 339.4 mW 
 P_out = V_out * I_out = 3.42V * 50mA = 171.0 mW 
 Efficiency = 171.0 / 339.4 = 50.4% --> very low efficiency
New LMR14010A:
No load:
 I_quiescent = 68 uA
With 50mA load applied:
 P_in = V_in * I_in = 14.38 V * 14.08 mA = 202.5 mW
 P_out = V_out * I_out = 3.28 V * 50 mA = 164 mW
 Efficiency = 164 / 202.5 = 81.0% --> consistent with Fig. 5-2 in the LMR14010A datasheet
Any thoughts on what may be causing the high power consumption / low efficiency in older devices? Thank you. 
  • 0
    TI__Genius 12475 points

    Hi Peter,

    Thank you for providing the details of your problem. I just had a couple of comments on your application:

    • The inductor current limit is a little low for this device. It should be at least as high as the high side switch current limit (1.5 A). In a thermal shutdown or a current limit condition this could cause damage to the device as the inductor saturates.
    • What is the diode current rating on D1?
    • Can you please share your application layout for the LMR14010A?
    • What is the ambient operating temperature of this use case?
    • Is there any condition in your application that may have caused some voltage overstress? It seems that something in the device's operation may have caused some overstress that damaged the device. The fresh device working on the same schematic makes this the likely phenomena. Please send waveforms of both the good and bad devices showing VIN, VOUT, SW, and CB if possible so we can observe the differences in their behaviors.

    Thank you,

    Joshua Austria

  • 0 in reply to Joshua Austria
    Prodigy 30 points

    Thanks Joshua for your quick reply. Please see my replies below:

    • The inductor current limit is a little low for this device. It should be at least as high as the high side switch current limit (1.5 A). In a thermal shutdown or a current limit condition this could cause damage to the device as the inductor saturates.

    Noted.

    • What is the diode current rating on D1? 

    D1 = Toshiba p/n CMS06. It's rated for 2A. 

    • Can you please share your application layout for the LMR14010A?

    Top:

    Bottom:

    Stack (ground and power planes in the middle):

    • What is the ambient operating temperature of this use case?

    ~10-60 degC for the units we pulled in from the field -- it's an outdoor application, so ambient temp can vary widely.

    • Is there any condition in your application that may have caused some voltage overstress?

    Not that we know of. The batteries are non-rechargeable, starting at 14.4V when fresh and going down from there. Occasional high-current demands on the battery cause its voltage to drop by 1-2 V, but it recovers quickly, and without spiking. Neither the battery nor the circuit have a low voltage cutoff. 

    • It seems that something in the device's operation may have caused some overstress that damaged the device. The fresh device working on the same schematic makes this the likely phenomena. Please send waveforms of both the good and bad devices showing VIN, VOUT, SW, and CB if possible so we can observe the differences in their behaviors.

    Bad Vin:

    Bad Vout:

    Bad SW:

    Bad CB:

    Good Vin:

    Good Vout:

    Good SW:

    Good CB:

    Notes:

    --Waveforms are from the two EVMs that I mentioned, with the following modifications from stock:

    R4 = 64.9k

    R3 = 19.6k

    L1 = 120uH (Wurth p/n 74404084121)

    R1 = 10k

    R2 = removed.

    --Please note the different timescales for the good (= 5 ms / div) and bad (= 1 ms / div) waveforms.

    Thanks. 

  • 0 in reply to Peter Russo
    TI__Genius 12475 points

    Hi Peter, 

    It looks like there is not something necessarily wrong with your schematic, but your layout is of some concern. Following the layout guidelines in section 7.4 of the datasheet is critical to ensuring that your device operates as expected. Prolonged operation of the device in a sub-optimal layout can cause damage to the device and/or harm its performance. I reviewed your layout, here are my comments:

    • The L1 inductor is recommended to be close to the SW pin to minimize magnetic and electrostatic noise. Putting the inductor on the opposite side of the board can potentially subject the sensitive traces, such as the FB resistor divider, to excessive noise that could potentially harm the device's regulation. 
    • It is highly recommended that the output capacitor, C17, is placed close to the L1 and D1 junction to reduce radiated and conducted noise.
    • Please see below for an example of a recommended layout:

    For more details, please see section 7.4 of the datasheet.

    Thank you,

    Joshua Austria

  • 0 in reply to Joshua Austria
    Prodigy 30 points

    Thanks Joshua. Yes, the layout is definitely sub-optimal. Unfortunately it's a legacy design, and the original designer didn't take much care with the layout of this and some of the other subcircuits...

    But, I wouldn't expect a bad layout to permanently damage / degrade the LMR14010A -- which is what we're seeing, because the old chips continue to underperform after being moved over to an eval board (which presumably has a good layout). And, in any case, we're also stuck with the bad layout for a while, on our existing devices.

    So:

    1. Are there any more tests we can do here to determine the root cause of the LMR14010A issue? 

    2. Can TI take a look at some of the parts we've pulled from the field? (if so, please let me know how to arrange for that) 

    3. Are there any pcb reworks and/or component changes that we can proactively make to our existing devices to prevent the issue from recurring? 

    4. Is there any benefit to replacing the LMR14010A on existing devices to LMR54410? 

    thanks,

    Peter

  • 0 in reply to Peter Russo
    TI__Genius 12475 points

    Hi Peter, 

    In my experience, layout does have the potential to permanently affect the device's performance as it could subject the device to stress that is not expected from a device in a normal operation. TI does not guarantee the performance of the datasheet for devices that are not in compliance with the datasheet recommendations. That being said, I see your conundrum and while I still stress that changing the layout is important, I will answer your questions:

    1. There are a couple tests that you can do to try and rule out some things if you have some Known Good Units (KGUs). You could try running a KGU with the EVM and your application and compare that with a KGU and your current design. You can use this analysis to try and pinpoint the biggest differences in performance between the two.
    2. You can submit the device for an Failure Analysis request, but as I have pointed out some critical issues with the layout, this process is likely to not yield any results that are unknown and the recommendations would stay the same. Analysis may show what has failed but our purview to as what could have caused it from failure analysis alone may be limited.
    3. I believe I outlined the biggest factors from a layout perspective that could affect performance. Maybe you can decrease the feedback resistances to reduce some noise coupling into the FB pin from the inductor, but this has a tendency to increase current consumption which would be counter intuitive to your use case.
    4. Replacing this device may help but even our newer parts have similar layout recommendations, so you may run into similar issues.

    Overall, I believe that the best advice that TI can give is to change the layout to be more in-line with the datasheet recommendations. If this is done and the part is not operating above the maximum ratings provided in the datasheet, the part should perform as expected.

    Thank you,

    Joshua Austria