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CSD85312Q3E: CSD85312Q3E common source question

Part Number: CSD85312Q3E
Other Parts Discussed in Thread: TINA-TI,

Tool/software:

Hi TI,

I have a application would be use back to back common source NMOS.

I would like to use 5V to turn on the back to back NMOS and without 5V the 3.3V would not leak to the Drain2 signal.Does the circuit make sense with that function?

Besides,as I know the NMOS turn on condition is VGS>Vth, but when NMOS is being off,  should it be floating in both source pin?

If it does, how could it work?It may a elementary knowlege but confused me for a long time, I would be grateful if you could help me to get it clearfy.

  • Hello Chien,

    Thanks for your interest in TI FETs. In most applications with a dual common source device, the common source terminal is left floating. To turn both FETs on, the common gate must be pulled at least 4.5V (lowest value of VGS where on resistance is specified in the datasheet and tested in production) higher than the highest drain voltage. Typically, one drain is connected to an input voltage and the other drain is connected to a load or output. When the common gate is pulled to a high enough voltage, the FETs will be on and the voltage at both drains and the common source will be approximately the same. If you have 3.3V at one of the drains and drive the common gate to 5V, then the common source will be at approximately 3.3V and VGS = 5V - 3.3V = 1.7V < 4.5V -> the FETs are not fully enhanced and Rds(on) is not guaranteed. Threshold voltage is the value of VGS where the FET just begins to conduct current and is specified at ID = 250μA. In order to guarantee on resistance VGS ≥ 4.5V. I hope this helps. Please let me know if you have additional questions.

    Best Regards,

    John Wallace

    TI FET Applications

  • Hi John,

    Thank you for your detailed explanation and help me alot! Here's still some questions as below:

    Since the application is not the power but the signal transfer, does Rds(on) guaranteed need to be required?Is it posible to just meet VGS>Vth condition?

    Regarding to the VS,  could you explain more how the VS voltage level could transfer from floating to the voltage in both drains and the common source are the same?

    Best Regards,

    Scott

  • Hi Scott,

    I think it's simpler to look at using a single FET as a high side switch where the drain is connected to the input voltage and the source is connected to the load. Essentially, the source is floating depending on the impedance connected to it. As the gate driven to a high voltage, the FET begins to turn on when VGS = VTH and the source voltage begins to rise up to the drain voltage. It is similar to the back-to-back FETs which prevent current from flowing when both FETs are off. I created a simple TINA-TI simulation of the DC transfer characteristics. The common source is floating and as the gate driven to a higher voltage, VGS rises and the FET begins to turn on at VGS = VTH. VGS remains flat until the gate voltage is about 5V and then starts rising as the FET becomes more enhanced (turns on harder). The voltage at the source is now fixed and further increase the gate voltage does not change the voltage at the source. The attached PDF includes the simulation circuit and the results. Let me know if you would like to try the simulation and I can provide it to you.

    The CSD85312Q3E is a power device that can conduct high currents. I'm not sure how well it will work to pass small signals. It is a relatively high cost part and I'm sure there are lower cost solutions. Have you considered using 2 discrete FETs like one of our FemtoFETs?

    Thanks,

    John

    CSD85312Q3E.pdf

  • Hi John,

    I think I've clarified it and appreciate your help!

    Thank you!

    Best Regards,

    Scott 

  • Hi Scott,

    Thanks for following up. I will close this thread.

    Best Regards,

    John