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LM5156-Q1: modulating the output voltage by injecting the control voltage to the FB network

Part Number: LM5156-Q1


Tool/software:

hi, 

am modulating the output voltage of the regulator the signal is a slow rising from 1V to 5V with a slope of 50Usec.

however, it rises correctly to the level with good control at full load of 500mA @ 35V, but when the signal changes to the other level of 1V the regulator enters in soft start mode and corruprt the operation.

how can i disable the SS?

the output capacitance is 1.22uF on a 70 Ohm resistive load.

i simulated it and is doing exactly the same thing of SS cicking in!

how can we get over the SS function?

cheers

Haider

  • Hi Haider,

    Thanks for using E2E.

    Could you please share your schematic, as well as the simulation files and your measurements of the issue you see?

    What are the specs of your design (Vin, Vout(range), Iout)?

    I am looking forward for your response.

    Best regards

    Moritz

  • hi 

    is ti ok if i send you the simulation files in Cadence?

    Vin = 24V with input PI filter

    VOUT range = 8 - 35V

    total load is 500mA

    control signal is 1-5V with an fall time and rise time of 50usec, i have to stick to these numbers as this is driving a transmission line to overcome line ringing.

    on the dropping edge am placing a sink load to decrease the discharge time of the output capacitor, its working, but i dont feel this is an efficient way

    will send you the schematics, the circuit is under design.

    also, for another issue, 

    the switching MOSFET has a leading pulse of a very high current which i think its due to the capacitance of the schottkey diode, is there a way to reduce that.

    i tried series resistor with the gate to slow down the switching time of the MOSFET but it does not help if its in the range of 1-5 Ohms, if you go higher the switching gets skewed and corrupted.

    is this a diode problem? can you suggest a diode with lower capacitance? if that was the problem!

    cheers

    Haider

  • hi Attached the schematic in PDF am running a simulation now will send the simulation once it ends

    how can i upload a file? 

  • Hi Haider,

    Thanks for the files.

    To reduce the large current spike, you can try to change the diode to an ultra fast silicon type. These have less junction capacitance.

    From the schematic i see that there is a resistor connected to the SS pin. This should be a capacitor.

    So what is the other issue related to the softstart? Im not sure if i fully understand what you mean.

    Best regards

    Moritz

  • Hi Moritz

    so when the SS is active and there is the SS capacitor, when the signal falls from 35V to 8 V the SS gets reset and the switching halts which disturbs the signal.

    also it happens when it climbs up and the it reaches its final 35 V level the SS resets and switching halts which causes big ripple.

    So to disable the SS I put a 300K resistor so even if the SS resets it only trips for 32uSec which does not effect a lot the signal shape and causes less distortion.

    my question is why the SS is resetting when there is a light charging to the capacitors?

    if I decrease the capacitors I have a large ripple.

    i Tried various fast recovery diodes but still the same response, is that the simulation? Or in fact it happens?

    cheers

    haider

  • Hi Haider,

    The reason for the softstart resetting is that there is an overvoltage detected at FB pin. To avoid the overshoot at the FB pin, you can slow down the ramp or make sure the output gets discharged fast enough when ramping the FB voltage up. Also you should connect the SS capacitor again (i used 10nF for the test) and have a longer delay time for your pulse voltage source. The sofstart should first be finished bofore manipulating th FB.

    Regarding the current spike when turning the switch on:
    This is the so called leading edge and the rootcause is that the parasitic switchnode capacitance (which consists of the diode capacitance, the MOSFET output capacitace and eventual capacitances due to the layout) is brutally discharged to GND. This cannot be completely avoided and there is also a leadink edge blanking time included inside the IC to not false trigger the current limit.

    Best regards

    Moritz