Tool/software:
Because I can not understand the UVLO threshold of TPS53317,
I referenced
Application Report
SLVA769A–April 2016–Revised September 2018
Understanding Undervoltage Lockout in Power Devices
www.ti.com/.../slva769a.pdf
and
Datasheet
TPS53317 6-A Output, D-CAP+ Mode, Synchronous Step-Down,
Integrated-FET Converter for DDR Memory Termination .
www.ti.com/.../tps53317.pdf
Could you help me to expain it?
Because there are not Vit+ and Vit- in the datasheet of TPS53317.I can not understand the FULL PERFORMANCE voltage of TPS53317,I want to confirm it.
During power up, I think the device may start functioning when VI ≥ 4.2 V, but it will certainly start functioning
as soon as VI ≥ 4.5 V. Full performance is only specified when VI ≥ 4.94 V.
Because the UVLO hysteresis is 440mV.
Is it right?
During power down, the device may stop functioning when VI ≤ 4.5 V, but it will certainly stop
functioning as soon as VI ≤ 4.2 V. Full performance is no longer specified when VI ≤ 4.94 V.
Is it right?
Thanks and Best Regards
Liang Chunli
