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TPS65216: DDR Power 1.35 V (DCDC3) Power Output Continues After Shutdown Command

R.Fukunaga
Expert 2665 points
Part Number: TPS65216
Other Parts Discussed in Thread: TMDSEVM437X, TPS65218

Tool/software:

Hi all,

About TPS65216

DDR power supply 1.35 V (DCDC3) output continues after shutdown command.

The connection between the PMIC and the CPU is described in the TI User Guide.

It is the same as TPS65216 Power Management IC (PMIC) With 4 DC/DC Converters, 1 LDO, and Integrated Power Sequencing datasheet (Rev. A).

There is no particular problem with the output waveform in the startup sequence.

Rails other than the DDR power supply are turned off in the shutdown sequence.

The same problem also occurs on TI reference board TMDSEVM437X.

Could you give me some information about the cause?

Best Regards,

Ryusuke

  • 0
    TI__Genius 11517 points

    Hi Ryusuke, 

    Are you able to clarify what is meant by "shutdown command"?
    How is power-down being triggered ?

    DCDC3 is intentionally set to remain ON if the PMIC is operating in SUSPEND/SLEEP mode to maintain power to the DDR memory.

    This could be the case, where PMIC is just in suspend mode, are you using I2C/ able to read the STATE bits of the STATUS register?

    If this is not the case, are you able to share waveform captures of startup/shutdown for DCDC3  (along with PWR_EN, DCDC2, DCDC4) ?

    Thank you, 
    Sarah 

  • 0 in reply to Sarah Lao
    Mastermind 6530 points

    Hi Sarah,

    Thank you for your supports.

    I am Ryusuke's colleague and am in charge of supporting the AM437x side.

    After the customer took the following measures, we confirmed that the DCDC3 output turned off during shutdown.
    Could you confirm the validity of this as a solution?

    • Fixed "STROBE(DC3_SEQ) = 5" in "tps65218_pmic_set_suspend_enable()" in "tps65218-regulator.c" in Linux SDK (v06.03.00.106).
      Originally, "STROBE(DC3_SEQ) = 0" was set in "tps65218_pmic_set_suspend_enable()".
    • Deleted "dcdc3: regulator-dcdc3" in "dts" in Linux SDK (v06.03.00.106).
      Deleted by referring to the E2E below.
      e2e.ti.com/.../linux-am4376-tps65218-dcdc3-issue
    Sarah Lao said:
    This could be the case, where PMIC is just in suspend mode, are you using I2C/ able to read the STATE bits of the STATUS register?

    The STATUS bit was set to 3h in the STATUS register.

    I have also attached the waveform just in case.
    [Startup sequence]

    Best regards,
    O.H

  • 0 in reply to O.H
    TI__Genius 11517 points

    Hi O.H, 

    Yes. The STATUS STATE bit being 3h does confirm the PMIC was operating in suspend mode. 

    And you did the correct thing to disable this function. 
    When DC3_SEQ = 0h, then the rail will not follow the shutdown sequence and remain on during suspend mode, 

    To change this, you would assign DC3_SEQ to a certain strobe, so it will follow startup/ shutdown sequence. By default, this should be at 5h, so DC3 will enable at strobe 5, as you currently have it. 

    This is the correct solution.
    No further action needs to be taken if you confirm the shutdown is now operating as desired.

    Best Regards, 
    Sarah

  • 0 in reply to Sarah Lao
    Mastermind 6530 points

    Hi Sarah,

    Thank you for your reply.

    I understood. Just to be sure, let me confirm one thing.

    It seems that DCDC3 is intentionally always ON in certain revisions, but am I correct in understanding that this behavior does not cause any problems such as malfunctions?

    If used in the default state, DCDC3 will be ON, but there is no mention of this in the data sheet or user guide, and it is different from the PMIC shutdown sequence diagram.
    Also, even in "tps65218-regulator.c" in the latest Linux SDK (v09.01.00.001), DCDC3 is ON in REV2.1.

    Best regards,
    O.H

  • 0 in reply to O.H
    TI__Genius 11517 points

    Hi O.H., 

    Yes, there is no issue with this behavior of DCDC3 being left ON. It was designed this way to keep the DDR memory powered and preserved.  

    There is a brief mention of this feature in the 1.3 Description section of the datasheet: (sleep mode = suspend mode)
    I do agree this should be made more clear, and the shutdown sequence diagram may be misleading, so I will personally look into getting the datasheet updated to also demonstrate when DCDC3 stays ON. 

    Best Regards, 
    Sarah

  • 0 in reply to Sarah Lao
    Mastermind 6530 points

    Hi Sarah,

    Sorry I missed it... I understood.
    Thank you for your kind supports!!

    Best regards,
    O.H

  • 0 in reply to O.H
    Expert 2665 points

    Hi Sarah,

    1)TPS65216 seems to transition to SUSPEND after shutdown command.

    Why does it not transition to PRE_ OFF?

    2)Is there any reason why TPS65216 protects memory after shutdown sequence?

    Due to RTC mode of TPS65218, does TPS65216 also act to protect memory in Default?

    Best Regards,

    Ryusuke

  • +1 in reply to R.Fukunaga
    TI__Genius 11517 points

    Hi Ryusuke, 

    1) TPS65216 will transition to SUSPEND instead of PRE_OFF if at least one of the outputs is not assigned to a sequence strobe. 

    Please ensure all outputs DCDC1, DCDC2, DCDC3, DCDC4, AND LDO1 have their "_SEQ" bits are set to a value between 3h to Ah (strobe 3 to 10)
    The device should then transition to the correct mode. 

    2) Power is provided to DDR so that DDR memory is set to be kept in self-refresh mode, retaining memory while consuming low power.
    Apologies since I am not as familiar with the DDR side of our portfolio, but I believe this is just a mode that is defined as a JEDEC standard. 

    I am not sure if I understood your question correctly, so please let me know if I can clarify more: 

    The TPS65218 has two more buck converters (DCDC5 & DCDC6) specifically for the RTC, powered by a backup battery to protect against power faults and remain always ON.
    But TPS65216 does not have these extra converters and therefore does not have this extra backup protection capability. 

    Best Regards, 
    Sarah

  • 0 in reply to Sarah Lao
    Expert 2665 points

    Hi Sarah,

    Thank you for your answer.

    1) I understand that if it is not set to sequence, it will be shifted to SUSPEND.

    2) I am sorry that my question is not clear.

    I would like to ask is do I need to power the DDR memory after shutdown? 

    I think you need to keep the memory powered when using in RTC mode.

    I thought that the function of TPS65218 with RTC mode was taken over and was set as a function of TPS65216.

    Best Regards,

    Ryusuke

  • +1 in reply to R.Fukunaga
    TI__Genius 11517 points

    Hi Ryusuke, 

    I understand. I do not believe you need to keep powering DDR memory after shutdown, but this would depend on your intended operation.
    I suggest looking into your specific processor requirements to confirm if this is needed or not, and whether/how this affects the device operation. 

    The TPS65216 is identical to the TPS65218, with reduced features. Note the difference in their applications here:

    Best, 
    Sarah

  • 0 in reply to Sarah Lao
    Expert 2665 points

    Hi Sarah,

    Thank you for your answer.

    Your prompt response is very helpful.

    Best Regards,

    Ryusuke