UCC21530-Q1: ucc21530 internal gate voltage booster and abnormal negative bias during DPT process

Hi Wang,

Thank you for your interest in our devices.

KaiKai WANG said:

1. according to the content of chapter 8.3.4 from datasheet, the driver output has an internal gate voltage booster function using an internal pull-up NMOS. My question is when to open pull-up NMOS and when to close the pull-up NMOS?

Both NMOS and PMOS are powered up at the same time. When the output rises, the NMOS has the least resistance path and allows more current to flow. As the gate of the MOSFET is charging, the gate-to-source voltage of this NMOS diminishes. At this point the PMOS offers the least resistance path and the NMOS is turning off.

KaiKai WANG said:

2. how to check if it's suitable to open the pull-up NMOS for i think drivers chip cannot measure the mos's gate voltage in order to know miller voltage drop period.

Refer to question 1 answer above.

KaiKai WANG said:

3. There has an abnormal phenomenon: during dual pulse test(lower mos as target device and upper mos is short-circuited with inductor) the upper mos's gate voltage will drop below 0V voltage rather than 0V when increasing DC link high voltage.

Is the high-side MOSFET shorted from gate to source? 

Would you be able to share more details on your test such as a setup/diagram and waveforms?

Thanks!

Regards,

Hiroki

DPT_questions.pdf

Hi Hiroki,

High-side mosfet's gate is not shorted. You can refer to the pdf file to get more details.

My question is why upper side mosfet(complementary) gate has a negative bias when testing lower mosfet.

Hi Sean,

yes, ch4's ground reference is directly behind the Ch2.

yes, in our driver design we use zener diode(the same as design in figure41) to generate negative drive voltage of mosfet and i know this design need hundred of microsecond to reach a stable status depending on mosfet gate discharging resistor.

I want to check if our mosfet could switch off safely with 0V drive voltage so in our DPT we were not generating stable negative bias by several pulses. As shown in pdf file we found different phenomenon when testing upper and lower mosfet. My question is why upper side mosfet(complementary) gate has a negative bias when testing lower mosfet.

Hi KaiKai,

I don't know why. Can you zoom out on your oscilloscope measurement and find where the negative bias starts on the low-side? Maybe the high-side common mode voltage step allows Cz to charge more quickly, whereas the fixed low-side voltage does not cause current to flow through the 2.5V zener.

-Sean 

Hi Sean,

I'll test it again. Here i describe this phenomenon briefly. When testing lower mosfet( upper mosfet is shorted with inductor), i found the complementary upper mosfet gate voltage drops from 0V to -2.5V when increasing dc link voltage about 50V. In our design, the zener diode has a nominal voltage 4.7V rather than 2.5V. Our single power supply is about 22.5V and to avoid voltage spike occurs at mosfet gate, we put a zener diode with 18V nominal voltage.

But when testing upper mosfet, the complementary lower mosfet gate voltage remains 0V when increasing dc link voltage.

i think maybe the gate driver causing this abnormal phenomenon but i don't know why until now.

Hi Sean,

i think whatever 0V or -2.5V is stable rather than transient voltage, i'll check it again.

pls refer to another pdf file, i have another question need your help. The question is why series bigger capacitor has bigger voltage in bootstrap drive circuit.

18V_bias.pdf

Hi KaiKai,

Again, this is an initial condition. These votlages should be analyzed after several switching cycles, not at DC or after a single pulse. The bootstrap supply requires the low-side switch to close in order to charge. 

At DC, the HV_DC link is probably floating, and it is slowly pulled up to 22.5-4.7V through leakage paths and the Zener diode.

Best regards,

Sean

Hi Sean,

I know the bootstrap drive and i met some difficult problems when using this method especially at DC condition.

As you said above, the dc link voltage will slowly charged up to 22.5V-4.7V, i want to know what's the charge path, could you pls describe this? I had marked every component's voltage drop on the figure(you can see the pdf file). The bootstrap capacitor only has 2.5V and DC link has 18V. The zener diode is not at reverse-bias status. All the input of driver chip is low and powered on normally.

As is shown in 18V_bias pdf file, my question is why bigger capacitor has bigger voltage when considering bootstrap and dc link capacitor are series connection?

Another question is when disconnecting bootstrap capacitor and driver chip(i mean remove the driver chip from PCB board), we can get right voltage divider phenomenon that's bootstrap capacitor has most of 22.5V. I want to know if driver chip has a voltage clamp internally(especially between pin 16 and pin14)?