Tool/software:
Attached below is the .zip file for the PSpice project that contains a few different schematics that allow for testing the driver and its characteristics with respect to operating conditions set forth by the desired application. The models are not exact representations of the silicon that will be in your system but this can provide a good idea as to what to expect when setting up a circuit with a half-bridge gate driver.
Typical Half-Bridge Test Bench.zip
NOTE: When adding measurement probes, place the probes at the pins of the IC to best understand the operation and characteristics of the gate driver.
Sync Buck Setup
The first test platform is that of the synchronous buck converter. This is setup with a 48V bus and default NMOS FETs. This is just an example of how a buck converter can be setup and it would be recommended to include additional components to complete the circuit for your actual design. These include but are not limited to RC filters on the inputs and turn off diode and resistors on the gates. For evaluating your system, it would be best to place the correct FETs into the circuit and adjust the component values to match that needed for your system. If using the correct FETs and circuit components, parameters like rise/fall times, delay matching and propagation delay can be checked.
Peak Output Current Setup
The peak output current setup platform can be used to test and understand a few different characteristics of the gate driver. These include but are not limited to peak driver output current, rise and fall times, as well as mimic system rise and fall times.
Peak Driver Output
Typically, TI’s half-bridge gate drivers are specified with peak current values for source and sinking at the output. This can be tested by adding a current probe at the LO and HO pins and switching the outputs high and low. These test parameters are outlined by the datasheet and can be implemented with the above PSpice model. The results and datasheet specs are also shown below.
Datasheet Rise and Fall Times
The rise and fall time specifications in the datasheet are outlined with specified loads with dictated thresholds. This can be checked on the model level by creating the same test characteristics as outlined by the datasheet. As seen below from the UCC27301A datasheet, rise and fall times are specified at both 1000pF and 0.1uF.
To test at these conditions, the load capacitors on LO and HO can be changed and simulated. Once simulated, you can zoom into the rising and falling edges to measure and see the rise and fall under the given conditions.
System Rise and Fall Times Check
In addition to testing the rise and fall times of the HO/LO channels with respect to the datasheet, the PSpice project also provides a platform for testing the rise and fall times based on a given gate resistance and MOSFET. This can also be calculated using the following tool:
[FAQ] UCC27282: Calculating Component and System Values for Designs Using Half Bridge Drivers
For using the PSpice model for determining rise and fall times, the gate charge of the chosen MOSFET will be modeled as a capacitor. In order to do that, you must find the effective capacitance of the MOSFET by using gate charge and gate-source voltage as seen in the equation below.
Once Cg is found, it can be inputted as the value for the LO and HO load capacitors and then the gate resistances can be manipulated to optimize rise and fall times. This will help give a good start on a resistance value to choose for your system design.
Switching between test platforms within the project
To switch from one test platform to the other, you must first make the desired project and schematic the root project as seen in the below image.
After doing that, the simulation profile must be selected and made active to go with its associated project. This is shown in the below image. Before simulating, ensure that the correct simulation profile is selected in the simulation toolbar.
