• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 64 subscribers
  • Views 354 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CSD15380F3: Leakage current for MOSFET

John Baczewski
Prodigy 20 points
Part Number: CSD15380F3

Tool/software:

I’m pleased that we’ve had great success in one of our mid-volume products using your Femto-FET MOSFETs.

 

I have a new design which will be a higher volume product, expected over 1 Million circuits.

The design has 3-4 similar circuits, all powered from a coin-cell which is regulated to 1.2v.  Ultra-low current draw is a key requirement.

It is a very critical design and needs to be extremely reliable and robust.

We plan to use both N-Channel and P-Channel MOSFETs in the design.  Key parameters are Vgs(th) and Idss and Igss leakage currents.  The operating environment is -40 to 100C.

 

I have successfully simulated over our entire temperature range for one of circuits using your N-Ch CSD15380.

The simulation model seems to do a great job at modeling Vgs(th) and both leakage currents, Idss and Igss, over our temperature range.

 

I’m aware that Vgs(th) has a negative temp. coefficient.  Most datasheets for MOSFETs doesn’t adequately cover leakage parameters.

Could you explain more about how leakage is modeled.  Is it based on measured data or does TI generate a simulation model based on knowledge of the fabrication of the device?

How well does that model for leakage take into account temperature affects?

How conservative is the model i.e. does it have adequate margin to account for fabrication process variations?

I’m not aware of any method to simulate both over temperature and across process variation.  However, what I’ve done is to simulate 30 degrees higher than our expected environment to ensure margin.

Would love to get feedback on this approach.

  • 0
    TI__Expert 7595 points

    John,

    Thanks for using our devices, John Wallace is far more familiar with the models than me and can give you an update on this when he returns tomorrow.

    Some other items you may find of interest, in the application note link here that contains all our web based technical content for MOSFETs in one document: https://www.ti.com/lit/an/slvafg3f/slvafg3f.pdf

    In section 4 there are 2 articles starting with the title "Whats not in the power MOSFET datasheet....", one is voltage variations and the other temperature.

    You may find this helpful/interesting

    Many thanks

    Chris....

  • 0
    TI__Mastermind 36140 points

    Hello John,

    Thanks for your interest in TI FETs. The PSpice models for TI FETs were created before I joined the product line and I was not involved in their creation. The models have been correlated for most of the datasheet parameters but unfortunately, not for leakage currents. I am waiting to hear back from a colleague who was more closely involved with the modeling of the devices on your questions. I'll update you as soon as I have more information.

    I have characterization data for samples from 3 lots over temperature collected during product development. I cannot share the actual data but I can tell you that the maximum measured value of IGSS at VGS = 10V and IDSS at VDS = 16V is much lower than the datasheet limit. Even at elevated temperatures up to 150°C the max measured value of IGSS < 5nA and IDSS < 40nA.

    Please keep in mind, this is for design guidance and TI only guarantees what is specified in the datasheet and tested in production. I hope this helps. Let me know if you need additional information.

    Best Regards,

    John Wallace

    TI FET Applications

  • 0 in reply to John Wallace1
    Prodigy 20 points

    Thanks John W. + Chris.  I'm encouraged by the measure data especially the results that were taken over temperature.  But 3 lots worth of data may Not sufficiently answer my concern.  As I previously stated, this is a high volume, high reliability product.  Leakage is a tricky parameter and I suspect it can be much worse if we have a bad lot (but still passing spec.).  I still have plenty of margin per the datasheet and the results you shared but I'm trying to ensure a robust design.

    Getting more details on the Spice modeling may give me the extra assurance that I need.  Looking forward to further discussion on this.

    John Baczewski

  • 0 in reply to John Baczewski
    TI__Mastermind 36140 points

    Hi John,

    I have confirmed with my colleague that there was no correlation done for leakage currents in the PSpice models. The models do not reflect actual leakage performance. I did some simple simulations and the leakages were much lower than the datasheet limits and the actual measured data. I have asked another colleague if he can provide distribution plots of IGSS and IDSS from production test data. I'll update you when I have more information.

    Thanks,

    John

  • 0 in reply to John Wallace1
    TI__Mastermind 36140 points

    Hi John,

    My colleague pulled the production test data for two wafer lots tested in 2023. There were just under 4 million pieces tested.

    • IGSS at VGS = 10V: average is 0.2nA, min is -3.6nA and max is 15.1nA.
    • IDSS at VDS = 5V: average -0.15nA, min is -35.6nA and max is 21nA.
    • IDSS at VDS = 16V: average is 0.87nA, min is -31.7nA and max is 40.2nA

    In general, the distributions look pretty tight but there are a few outliers that still pass the datasheet limits with some margin.

    I'm curious how you are driving the FET since your battery voltage is 1.2V. Rds(on) is specified to a minimum VGS = 2.5V. With VGS < 2.5V, the Rds(on) curve shown in figure 5-7 of the datasheet becomes almost vertical. In order to guarantee Rds(on), VGS >= 2.5V. TI has other N-channel FETs with Rds(on) rated down to VGS = 1.8V but nothing lower.

    Thanks,

    John

  • +1 in reply to John Wallace1
    Prodigy 20 points

    Would still like some feedback on Spice model for leakage.  

    In other posts, you seem to reference TI's 2 part article SZT206.  That article does a good job discussing leakage and how it increases exponentially over temp.  But all the data in the article is at 80% Vds for Idss and 100% Vgs for Igss.  My design only requires ~ 15% Vds and 25% Vgs. This can have a big impact.

    Finally, I did simulate at 80% Vds and 100% Vgs but I didn't see the exponential increase in leakage vs. temp.  On a positive note, I did take the measure data you provided above and 2.5x factor and compared that with the simulation results up to 140C.  The simulation was comparable and maybe slightly worst-case which gives me confidence in the simulations I ran.

  • 0 in reply to John Baczewski
    TI__Mastermind 36140 points

    Hi John,

    The PSpice models have not been correlated for temperature or voltage. I have confirmed this with a colleague who was involved in the FET designs and modeling efforts. The best I can do is provide you with data. I don't want to share the data on this public forum and will email you directly.

    Thanks,

    John