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TPS7A47: PLL & CB Power Supply Design verification

Haritha Munnangi
Intellectual 280 points
Part Number: TPS7A47

Tool/software:

Hi Team

Please help to review the design below and provide your feedback.

1) 3V3_PLL

Part number: TPS7A4701RGW

Input Voltage: 6.5V

Output Voltage: 3.3V

Load current: 377mA

Application: PLL Input

2) 2V5_CB

Part number: TPS7A4701RGW

Input Voltage: 6.5V

Output Voltage: 2.5V

Load current: 607mA

Application: PLL Clock Buffer Input

Thank in Advance,

Regards

Haritha

  • 0
    TI__Guru 50025 points

    Hi Haritha,

    For 1), I calculate the output voltage to be set to 1.4V + 1.6V + 0.4V + 0.2V + 0.1V = 3.7V. They need to remove the connection to pin 10 (0P4V) for a 3.3V output. I want to also note that the startup time with CNR = 1uF is about 50ms. This isn't an issue, just want to make sure they understand this. 

    For 2), I calculate the output voltage to be set to 1.4V + 1.6V + 0.8V + 0.2V + 0.1V = 4.1V. They need to remove the connection to pin 8 (1P6V) for a 2.5V output. Same note for the startup time. 

    Everything else looks good.

    Regards,

    Nick

  • 0 in reply to Nick Butts
    Intellectual 280 points

    Hi Nick,

    Thanks for the quick reply.

    1)Resistor R618(DNP) which is connected to pin 10 of IC will not populate in PCB (BOM Quantity is 0)

    2)same with second IC - Resistor R615(DNP) which is connected to pin 8 of IC will not populate in PCB (BOM Quantity is 0)

    We need startup time should be less than 5ms, so it ok CNR if we change to 0.1uF??

    Thanks & Regards

    Haritha

  • 0 in reply to Haritha Munnangi
    TI__Guru 50025 points

    Hi Haritha,

    The datasheet has the equation to calculate the startup time. With 100nF, the typical startup time for the 3.7V output is 10^5 * 100nF * ln((3.7 + 5)/5) = 5.5ms, and for the 4.1V output is 10^5 * 100nF * ln((4.1 + 5)/5) = 6ms. You will need to use a smaller CNR and note that this is a typical startup so you will want to add margin as well. 

    Regards,

    Nick