Part Number: TPS54160A
Tool/software:
I'm confused by the power good operation when running TPS54160A with a negative output voltage. I would have assumed that power good be de-asserted because the VSENSE-GND votlage is 0.8V. It's just that GND is at -12V. However it appears tha
t the power good pin is being asserted. Any ideas why? Schematic to the right:
Hi Dan
Thanks for writing to us. Your assumption about power good status is correct, once the VSENSE pin is between 94% and 107% of the internal voltage reference the PWRGD pin is de-asserted and the pin floats. Although in your circuit when PWRGD pin is de-asserted, pin voltage with respect to Vout will be 3.3 -(-12) = 15.3 V which is greater than absolute maximum rating of PWRGD pin (6V). This can be avoided by using level shift circuit shown in Working with Inverting Buck-Boost Converters (Rev. B). Moreover, you can add R1 to the circuit as shown in attached figure. Value of R1 should be chosen in a manner to keep voltage of power good below absolute maximum rating and above the threshold of Q1 when PGOOD is de-asserted.
I hope this resolves your issue.
Thank you
Onkar
