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TPS736: Can Ven be greater than Vin?

Austen Royer
Prodigy 110 points
Part Number: TPS736

Tool/software:

Hello!

I am testing the TPS736 in a design, where I am supplying 3.3V to the VIN pin in order to generate a 1.8V output rail. I notice in the datasheet that VEN is typically between 1.7V and VIN for enabling the LDO, but I am driving the VEN pin with 5V and seeing nominal behavior, and am not seeing the VEN signal get shunted or clipped down at all. Since the IC is compliant to CMOS logic levels, is it acceptable to have VEN be at a higher voltage than VIN, so long as it is still within maximum operating conditions? Is there any damage done to the chip if VEN is 5V while VIN is 3.3V? Or is the lifetime reduced by this sort of setup?

Thanks

  • 0
    TI__Genius 14245 points

    Hi Austen, 

    I'm updating the answer here to be more complete. 

    Yes it is acceptable to have Ven>Vin as long as Ven remains below the maximum operating voltage listed in the datasheet (5.5V). There are no long time reliability concerns if Ven=5V while Vin=3.3V, this is indicated by the abs max table which states that Ven can support 6V and there is no dependency on Vin. 

    This EC Table uses an older format which places Vin as the maximum value for Ven(high). We have stopped using this format as it can cause confusion with customers thinking either the LDO may enable anywhere between 1.7V and Vin (this is not true) or as you indicate may be damaged if Ven exceeds Vin (this is also not true).

    For TPS736 the maximum threshold is 1.7V (it could be enabled between for values between Ven(low)=0.5V and 1.7V) but Ven can be taken all the way to 5.5V regardless of Vin.