TPS746: TPS746 Voltage margin transition and Vdropout

Hi Neo,

            Just to confirm, is the min ambient temperature -5°C and the max ambient temperature 65°C? At 0.75V V_OUT, I do not see a risk of the device entering dropout. The device would shut off and V_OUT would collapse only if the device enters thermal shutdown or is disabled via the EN pin. Would it be possible to capture some scope shots showing V_IN, V_EN, I_OUT and V_OUT when this shutdown happens? Thanks!

Regards,

Srikanth

Thanks Sriknth.

Yes the min ambient is -5C and max is 65C. 

Considering worst case, Vin is 1.74V while Vout is 0.77V, do you see any risk?

For LDO we can not measure the current.  This issue is very difficult to repro. so far we only saw issue happened after 47 loops of HV->LV margining.

Will Vout voltage margin from high to low trigger anything? we implemented voltage margin in this way as shown as below.

Thanks

Hi Neo,

            I am not sure I understand how the margin is being controlled. I assumed the variation was coming from the external feedback resistors. Are you applying an external voltage at the FB/NC pin? Could you provide more details in the methodology? Do you see this issue across multiple parts?

Regards,

Srikanth

Hi Srikanth,

We are doing voltage margin similar as the way stated in below TI document. The only difference is in my design, the power sequence works as a DAC which provide a voltage to FB node through a trim resistor. (see snap shot provide earlier).

1. Initially, the DAC is hi-Z output so nominal 0.75V can be achieved.

2. Then, a voltage lower than Vref is generated at the DAC output which trims the Vout to be 0.75V+3% through the trim resistor 13.7Kohm.

3. After that, a voltage higher than Vref is generated at the DAC output which trims the Vout to be 0.75V-3%.

After step3, We observed TPS746 LDO Vout collapses and UV fault is reported to power sequencer.

https://www.ti.com/lit/an/sbaa341b/sbaa341b.pdf?ts=1729128913707&ref_url=https%253A%252F%252Fwww.google.com%252F

Thanks

Neo

Hi Neo,

            Thanks for providing the details, I will look into this and get back to you. 

Regards,

Srikanth

Hi Neo,

           Has this issue been observed across multiple units? 

Regards,

Srikanth

Hi Srikanth,

Yes, the date code of TPS761 is 2246. We are still working on root cause of this issue.

Are you able to get the sample with same date code and verify?

Thanks

Hi Neo,

            I apologize for the delay in getting back to you, I was out of office last week. We will not be able to replicate the issue, since we do not have the setup to do so. If this issue has been observed across multiple units, I suspect that the part is entering into some kind of test mode. Could you share clean scope shots of V_IN, V_EN and V_OUT? I am looking to see if there are any glitches on the voltage lines. Thanks!

Regards,

Srikanth