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BQ25125: Schematics for VSYS at 1.8V and LDO at 1.8V

Florian Zierer
Prodigy 50 points
Part Number: BQ25125

Tool/software:

I want to use Vsys with 1.8V and LDO with 1.8V which seems to be the default setting for BQ25125 as written in the device comparison table in the datasheet.

I have some questions:

1. The typical application example connects SYS and VINLS. The table "Electrical characteristics -> LS/LDO Output" says 2.2V are required on VINLS for LDO operarion.
- Does it work when SYS and VINLS are connected to get 1.8V on LDO?

2. Chapter 9.3.21 says "If the output of the LDO is less than the programmed V(SYS) voltage, connect VINLS to SYS. If the output of the LDO is greater than the programmed VSYS voltage, connect VINLS to PMID."
- In our situation, VLDO and VSYS are equal. Should I connect VINLS to SYS or PMID?

3. VINLS does not have a capacitor in the typical application but the datasheet says "Connect 1 µF of effective ceramic capacitance from this pin to GND".
- Do I need the capacitor?
- Is it also required even when PMID is connected to VINLS? PMID already has a 4,7µF capacitor.

  • 0
    TI__Genius 15095 points

    Hi,

    1. Yes this should work, I recommend putting LDO in passthrough mode for the most efficient operation.

    2. You should be able to connect VINLS to SYS for more efficient operation. Keep in mind that current pulled through the LDO will also be pulled through SYS. If SYS current is a limiting factor and you plan to pull a lot of current through the LDO then you may consider connecting VINLS to PMID instead.

    3. Typically VINLS does need a capacitor that to supply LDO, but if connected to VSYS then it should be sufficient unless you expect high transient current draws from VLDO.

    Best Regards,

    Juan Ospina