LP3856-ADJ: Designed circuit is feeding power to the output port of the device

Hi Armin,

Do you have any estimation of the leakage current onto the output? If the leakage is on the order of a few milliamps or less then it's likely not much of an issue. Is the device still able to start up from the negative output bias condition? 

Regards,

Nick

Hello Nick, 

We cannot probe the current directly as this is currently on a high density PCBA. But we do have a network with resistors in the kOhm range in series within this path so we suspect that the current would be in the mA or uA range. We have had no issues with the device starting up. 

Hi Armin,

My only concern in that case is that I would think that the current into the OUT pin through the ESD cell would seem to need to be more than uA range because the ESD cell when forward biased has a similar I-V curve as a standard diode, so for the voltage to be steady at -0.54V I would think that the current must be more substantial than that. If you can be confident from your design that the current is in fact small like you mentioned, then I don't think it's a concern. Just something to think about. 

Regards,

Nick

Hello Nick, 

We ran some LTSpice simulations with our full circuit under the assumption that the Vout port would appear as an open circuit. Given the block diagram and the fact that it is on the drain of a p-channel mosfet, this assumption should be right. The simulation shows that our currents are within the uA range and our voltages line up within 0.02V. If this sounds fine, I would be happy to consider this resolved.