TPS62873-Q1: schematic review

Hello Adrian,

Thanks for reaching out to us.

Will provide feedback tomorrow on the schematic.

Best regards,

Excel

Hello Adrian,

Please resend a clear copy of the schematic and PCB layout so I can review it properly.

By the way, can you respond on the items below?

1. Only U9 was damaged? Are there other components that were affected? 

2. At what application condition U9 was burnt?

3. Did the board works fine after replacing U9?

4. How many units have the same failure issue?

5. What is the project stage (EVT, DVT, Masspro)?

6. Can you provide a photo of the IC top marking?

7. Did you send the IC for FA?

Thank you.

Best regards,

Excel

Hi Excel,

Pls check a clear version below:

失效分析电路.docx

For the question u listed, please see my reply below:

1. Only U9 was damaged? Are there other components that were affected? 

[Adrian]: Yes, only U9 was damaged. Customer changed another new TPS62873 while keep other components, the vout showed normally.

2. At what application condition U9 was burnt?

[Adrian]: It was a adopted in Mass product, their customer reported the product can not bring up in daily use. And we just found U9 was damaged after tear down.

3. Did the board works fine after replacing U9?

[Adrian]: Yes.

4. How many units have the same failure issue?

[Adrian]: So far only 1pcs.

5. What is the project stage (EVT, DVT, Masspro)?

[Adrian]: Masspro

6. Can you provide a photo of the IC top marking?

[Adrian]: Top marking show: 873Y1B-TI 2BF-852KG4

7. Did you send the IC for FA?

[Adrian]: Not yet. 

BR

Adrian

Hi Adrian,

Thanks for the feedback.

First, the The schematic diagram looks fine except that the resistor in series with EN pins need to be >= 15kohm (see figure below).

For the layout, the first item I noticed is that U9 was placed in between U7 and U8 considering it needs to be positioned after U8. Can you ask the customer to send us a copy of the complete PCB layout (all layers) of VDD_CPU_AVS rail so I can check it in details? In addition, I think it's best to send the NG unit for failure analysis to determine if the damage was related to electrical or mechanical stress considering there's no evident of burst mark on the top package.

Best regards,

Excel

Hi Excel,

The previous schematic had network pagination and was not captured completely. In customer's design, a 20kΩ resistor is connected in series at the En pin, which is in compliance with the design specifications.

The output of the subsequent stages of U7, U8, and U9 are all part of the same network, and the order of positions should not affect the operation of the chips.

Moreover, all other cECUs that have been produced and shipped with this design have not exhibited any issues with the BUCK being burned out.
Please find the layout wiring in the attachment and kindly analyze and provide feedback as soon as possible.

VDD_CPU_AVS网络走线.pdf

Thank you

BR

Adrian

Hi Adrian,

Thanks for updates.

The U7, U8 and U9 placements should not affect the converters operation. However, it could influence the current sharing between the buck ICs. Anyway, I have additional items need clarification. See details below.

1. How the VIN (in yellow) of U7, U8 and U9 connected to VCC_3V3_TDA rail? At what PCB layer?

2. Ask the customer to measure the inductor currents of L148, L149 and L150, and VIN voltage across U9 (use the tip and barrel method) using the NG (failed) board simultaneously in one waveform . The intention is to check for inductor current imbalance.

3. What is the failure analysis status? Please share the document once available.

Best regards,

Excel

Hello Adrian,

Just a gentle reminder.

Any updates on the queries from my previous post?

Best regards,

Excel

Hi Excel,

Pls check my updates below.

Excel Regidor said:

The U7, U8 and U9 placements should not affect the converters operation. However, it could influence the current sharing between the buck ICs.

Is there any design guidance document on how the position sequence affects current sharing? Please provide it, thank you~

Excel Regidor said:

1. How the VIN (in yellow) of U7, U8 and U9 connected to VCC_3V3_TDA rail? At what PCB layer?

Pls check the layout as below attachment.

失效BUCK layout分析.pdf

Excel Regidor said:

2. Ask the customer to measure the inductor currents of L148, L149 and L150, and VIN voltage across U9 (use the tip and barrel method) using the NG (failed) board simultaneously in one waveform . The intention is to check for inductor current imbalance.

1. The VCC_3V3_TDA voltage is measured as follows: the peak-to-peak value is 67.08mV;

2. We tested the output current of the three cascaded BUCKs in various application scenarios.

The test results show that U7 has the largest current, U8 and U9 are almost the same, with no obvious difference. The detailed data are as follows:

BR

Adrian