TPS7H4001-SP: How does paralleling devices NOT affect minimum output voltage?

Hi Lauren,

Is this question related to this other E2E post? 

When paralleling these converters, each one is acting as a separate source, and their currents are being combined at the output. Since each device is independently switching at it's own frequency, with it's own duty cycle, and has it's own output filter, no change in minimum output voltage is needed to stay above the minimum on-time of each individual device.

Thanks,

Andy 

Hi Andy, yes it is, I took over for Jim. I couldn't find his previous thread so just started a new one. 

Another question on this-

Regarding the worst case current sharing- since there's no current sense/sharing line or other communication between paralleled IC’s, they're concerned about current sharing during dynamic loads, and also if the power stage transconductance (gm) variation fully addresses possible steady state mismatches. (Bounding the current share mismatch using gm variation is mentioned in the 4001 quad eval board datasheet and similar devices like the 4011 datasheet)

 Is there any data on current sharing performance of 2 or 4 parallel 4001 ICs during dynamic load steps that you have and could provide?

And also, any example analyses or further information on how just considering the gm variation would effectively fully account for current sharing mismatches in steady state?

Hi Lauren,

Unfortunately, we have not collected data regarding current sharing performance during dynamic loads / load steps. However, I would not necessarily expect any issues or significant variation beyond what has already been shown for steady state / static loads. There are, of course board-level load step waveforms published in the TPS7H4001QEVM-CVAL User's Guide, but they do not show current sharing between the channels.

We can consider gmps (power stage transconductance / COMP to Iswitch gm) variation to be responsible for nearly all current sharing mismatches between devices because the COMP pins of the devices are connected together. Since COMP is the output of the error amplifier, each device in the parallel system is effectively getting the same error amp signal. The only major variation left to introduce error in the output current of the devices is the power stage transconductance (gmps), which relates the voltage at the output of the error amp (COMP) to the current through the FET.

Thanks,

Andy

Hi Andy,

Thanks for the help so far. Some additional follow-up questions:

For the steady state sharing mismatch, they're imagining an ideal verification would be a lab test measuring the COMP to Iswitch gm of 4 ICs at various loads, then measuring the current sharing between those 4 ICs at each load, and then verifying how fully the gm differences do account for any sharing mismatch.

Is there any test data or documentation that already does that verification, or could be used to support it?

They see that the COMP to Iswitch gm had to be measured to define the datasheet ranges, and the quad eval user’s guide measured sharing mismatch at multiple loads, they're just not sure if we'd have data from doing both with the same parts.

Thanks,

Lauren