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TPS38700: Application question in optical amplifier during upgrade process

Part Number: TPS38700
Other Parts Discussed in Thread: TPS389006

Tool/software:

Hi Team,

Could you help answer below questions regard TPS38700?

1. Can TPS38700 still have consistent output during the upgrade process?

2.What gonna happened when TPS38700 upgrade failed?

3.What is the IO status of TPS38700 during upgrade?

4.What is the default timing of TPS38700

5.Do we have any other new sequencer that can promote to customer?

Thank you,

Yishan Chen

  • Hi Team,

    We have a meeting with customer about this device today.

    If we solve these concerns of customer then we can we can win this devices in today.

    So please give a quick respond on these question, we can also align a meeting to discuss if needed.

    Thank you,

    Yishan CHen

  • Hi Yishan,

    Thanks for your question!

    1. Can you please explain what you mean by "consistent output" and "upgrade process"? Does upgrade process refer to up sequencing, and what consistent output is the customer looking for?

    2. If upgrade means up sequencing, if an ENx pin has an error (if it should be low and is high or if it should be high and it is low), then the TPS38700 will detect this and assert NIRQ. The error will be logged at register 0x10 bit 2 (F_EN).

    3. Table 6.1 from the datasheet below shows the pin functionality where all ENx and GPO pins are outputs. ENx pins go high with the sequencer timing while the GPO pins act as MCU output pin extenders.

    4. The currently released TPS38700 has timeslots of 625 us with the following up and down sequencing.

    In this device, each power up time slot takes 625 us, so PWR_EN1/2 will activate in the first 625 us and PWR_EN3/4/8 will activate in the following 625 us time slot.

    5. The TPS38700 and TPS38700S are the only two sequencers currently released, and the TPS38700S can be paired with the TPS389006 in order to provide high accuracy monitoring to the sequencing process. ENx pins in the TPS38700 can be from 1-12 channels and depending on the business case, a custom OTP can be created for the TPS38700 for the customer.

    Please let me know if you have further questions, and I hope this helps!

    Best Regards,

    Andrew Li

  • Hi Andrew,

    Thank you for your support.

    The upgrade here means MCU update the bits in register. So the first question will be:

    (1) What is the GPIO status when I2C write the bits in TPS38700, Could TPS38700 still keep the same EN sequence here>

    (2) What if I2C communication fail or write wrong frequency, do we have any protection mechanism in that situation?

    (3) Is TPS38700 only support OTP, Could we refresh the default register without I2C communication?

    Thank you,

    Yishan Chen

  • Hi Yishan,

    Thank you for the clarification!

    1. ENx pins will be held at their current state when there is an I2C write to the TPS38700, but I2C changes will be saved in the registers and take effect on next operation. For example, if the ACT pin is high and up sequencing has already occurred, any changes to up sequencing will take effect the next time an up sequence occurs. In this situation, if down sequencing is changed after up sequencing has already occurred, it will take effect immediately at the next down sequence.

    2. Could you please provide some more explanation to what you mean by "write wrong frequency"? In general, built in self test (BIST) ensures that internal operations function as intended and SDA and SCL mismatches may come as a result of some delay from the board.

    3. The TPS38700 does not have any non-volatile memory (NVM) so changes to the OTP cannot be saved after the device has shut down. The default operation of the TPS38700 is from the OTP, and any desired changes must be made via I2C communication.

    I hope this helps!

    Best Regards,

    Andrew Li