Tool/software:
Test conditions : 812VDC, full load is 43A @Vout 23.5V
Below are images at different loads and different delays. I'm testing with different delays and different shim values.
Yellow: transformer primary voltage
Blue : transformer primary current
Purple, green: synchronous FETs drain source
1. VIN : 812 VDC, DELAB : 8.2K , DELCD: 8.2K , DELEF : 8.2K
LOAD : 25.8A, Llkg + shim : 22.6uH + 20uH
2. VIN : 812 VDC, DELAB : 8.2K , DELCD: 8.2K , DELEF : 8.2K
LOAD : 25.8A, Llkg + shim : 22.6uH + 30uH
3. VIN : 812 VDC, DELAB : 8.2K , DELCD: 8.2K , DELEF : 8.2K
LOAD : 33A, Llkg + shim : 22.6uH + 30uH
I want to understand the flat region in current and why the dip in that region by increasing current . What is happening and what more can be done to make the design better. ?