CSD23280F3: Issues using the PMOSFET as battery reverse protection

Hello Francisco,

Thanks for the inquiry. Can you please share your schematic. If you do not want to share on this public forum, you can send it to me via private message. I sent you a friend request. The CSD23280F3 is a chip scale device with land grid array (LGA) solderable pads. There is no plastic encapsulation. Because this is a silicon die with solderable pads, we advise against probing the body of the device as it can be chipped or cracked which can affect the electrical performance of the FET. From your description, it sounds like the FET is not turning on. Have you confirmed VGS is at the proper voltage? When voltage is applied at the drain, initially the body diode of the FET will conduct pulling the source voltage higher than the gate which will turn on the FET. There should be minimal voltage drop from drain-to-source when the FET is on. If the FET is not on, then the drop from drain to source should be about a diode drop. Did you follow the recommendations for the PCB footprint and stencil openings in the FET datasheet? This is critical to successfully assembling these FETs onto your board. The body (substrate) of the device is electrically connected to the source of the FET. I look forward to your response.

Best Regards,

John Wallace

TI FET Applications

Thank you John for your response,

We decided to deleted the CSD23280F3 from our design and return to our previous DMG2305UX PMOSFET. At the current status of the project we can't waste time looking for this issue. But still I would like to understand the origin of the problem.

- Related to footprint, we followed the recommended pattern on page 9 from the data sheet. I just payed attention to the stencil pattern on same page and see that solder mask edge doesn't match with the pad itself? 

- Indeed the problem is that the FET is not turning on but I dont understand why some PCBs work well and others not. Maybe a problem during assembly happened and the part was damaged but while visual inspection with microscope we didn't find any difference between PCBs that work and others that didn't.

- I consider that a voltage drop between drain and source of 0,2V is a very high drop for our application. Again, this voltage drop doesn't appear while using DMG2305UX under exact same PCB and conditions

- Noted, the body is connected to source

Regards

Hi Francisco,

I'm sorry to hear that you're removing the TI FET from your design. Perhaps when there is more time on another project you might reconsider. With regards to the stencil design, please see the FemtoFET SMT guidelines at the link below. TI recommends solder mask defined (SMD) pads over non-solder mask defined pads. The offset of the stencil on the two smaller pads is to improve solder paste transfer efficiency. It also maintains the separation between the pads to prevent solder bridging. As I mentioned in my previous response, this is a chip scale LGA part and as such, care must be taken during assembly to prevent chipping and/or cracking of the die. We have seen performance degradation in the form of higher leakage currents due to mechanical during assembly and handling. The second link below is to an app note on solving assembly issues with these devices. I agree that 0.2V is excessive in your application where the FET is supposed to be on. That's why I asked you to check the gate voltage to see if it is actually low enough. If not, that may provide some clues as to what is happening in your application. Please let me know what else I can do to support you.

https://www.ti.com/lit/ug/slra003d/slra003d.pdf

https://www.ti.com/lit/pdf/slvafh0

Thanks,

John

Hello Francisco,

Following up to see if your issue has been resolved. Is it OK to close this thread since you're removing the TI device from your design? Please let me know.

Thanks,

John