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TPS782-Q1: TPS782-Q1 Pspice model - negative current Iout

Oscar Liborio
Prodigy 730 points
Part Number: TPS782-Q1

Tool/software:

Hello,

 

My costumer is using our model for their simulation with QSpice.

When the EN signal goes low a low impedance path between OUT and GND seems to appear causing a large negative Iout (fast drop of Vout).   

 When testing the real device this behavior is not observed (slow fall of Vout - internal RDS off > 1Mohm)

 

Is this discrepancy between simulation and real measurements related to our simulation model (TPS78230.- [Version 2.0 Jan 2014])?  

 

Thank you in advance.

 Oscar

  • 0
    TI__Guru 50025 points

    Hi Oscar,

    Yes, the PSPICE model for this device is a legacy model that has imperfections and can have unrealistic results. When disabled the output becomes high-impedance and does not sink current. 

    Regards,

    Nick

  • 0 in reply to Nick Butts
    TI__Prodigy 730 points

    HI Nick,

    I see that on ti.com there is a revised version available. Has the behavior been corrected there?

    Would it take much time to correct the model, for the simulation to match the real behavior of the device? 

    The costumer would like to run simulation at edge conditions for a more reliable design.

    Bests

    Oscar

  • +1 in reply to Oscar Liborio
    TI__Guru 50025 points

    Hi Oscar,

    It's unlikely that the Rev A will have fixed it. It's a huge effort to create LDO models that accurately reflect device behavior, and we are working on ways in which we can improve them. This is a project that will take on the order of months to years to have a better model, and more time than that to make models for each of the ~600 devices that we have. So unfortunately there isn't a lot that can be done to help them simulate more accurately on their side. 

    Regards,

    Nick

  • 0 in reply to Nick Butts
    TI__Prodigy 730 points

    Hi Nick,

    I understand.

    Looking at the circuit above would it make sense to insert an ideal switch in front of R1 which goes open when EN is low, in order to avoid in the simulation negative current flowing back into the LDO? (I am not familiar with spice simulation so i don´t if this is possible)

    Or can you suggest a similar device with a model not showing this bug?

    Regards 

    Oscar

  • 0 in reply to Oscar Liborio
    TI__Guru 50025 points

    Hi Oscar,

    That could work in the case that VIN stays higher than VOUT. A real device would sink current if, for example, VIN collapsed (disabling the device) while VOUT stayed high, and with a switch there it would block current from sinking. 

    Our models are mostly derived from the same architecture, so they will likely all share similar characteristics. This is a known limitation of our LDO models.

    Regards,

    Nick

  • 0 in reply to Nick Butts
    TI__Prodigy 730 points

    Hi Nick,

    Ok , would the LDO sink current even in the disabled state (EN = Low)?

    Thanks,

    Oscar

  • +1 in reply to Oscar Liborio
    TI__Guru 50025 points

    Hi Oscar,

    If you are referring to the case that VIN collapses while VOUT is high, the current flow into OUT is through the intrinsic body diode of the pass FET, so current will conduct (in most devices that do not have intentional circuitry to prevent it, which most devices do not have) regardless of the EN status.

    Regards,

    Nick