Tool/software:
Am I right to consider the capacitor across the REGSRC pin and VSS as a bootstrap capacitor for enabling the FETs? Right now, I have 1uF and 4.7 uF across REGSRC to VSS. Currently, my design has 10 CFETs in parallel and 10 DFETs in parallel (not all shown in attached image). The CFETs are being driven through the suggested PFET circuit, and the DFETs are driven by an external driver. The Qg for the FETs being used is 81nC. Therefore, the total gate charge is 810nC on CHG and DCHG, 1620nC combined.
I know generally the charge source for driving the FETs should be at least 10 times bigger than the total Qg.
- Should I increase the capacitors across REGSRC to VSS to account for the combined gate capacitance?
- Do I need to account for the combined (CFET and DFET) gate capacitance, or since the DCHG FETs are being externally driven, I only need to be concerned with the CHG FET total gate capacitance.
- Is there anything else I could do to improve my FET circuit shown below?
