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TPS25830A-Q1: Effects of Improper Attachment and Solder Coverage Variations on Exposed Thermal Pad

Part Number: TPS25830A-Q1

Tool/software:

Hello TI,

We are currently reviewing the design and SMT process of the exposed thermal pad of TPS25830A-Q1 in our application, and we have some questions below:

  1. What are the potential impact if the exposed thermal pad is not properly attached to the GND plane during SMT soldering process?
  2. How does the solder coverage percentage on the exposed thermal pad affect thermal dissipation and other key performance parameters?
  3. Are there specific guidelines or benchmarks for solder coverage that we should follow to ensure optimal performance and reliability?

Thank you.

Many thanks,

Peter Wu

  • Hello Jheng-Wei,

    We will look into this one and get back to you shortly.

    BR,

    Seong

  • Peter,

    The ground plane solder pad is critical for 2 purposes:  It provides the main path for the buck converter return path and It is the main IC thermal conduction path into the PCB (As you listed in question 2)  I suspect that the USB switch performance would have the greatest degradation in performance followed by the buck converter efficiency and thermal performance, I do not have easy access into the specific benchmarks that you are asking about, but the footprint that is present in the datasheet and the footprint that TI utilizes on the EVM represent the attach methodology that TI recommends.  

    Deviating from this attachment methodology is strongly discouraged.

    Regards,

    Chuck

  • Hello Chuck,

    Thanks to your reply. We appreciate the explanation of its critical roles in thermal conduction and as the main return path for the buck converter.

    However, we would like to seek further clarification on the following points:

    1. Solder Coverage Percentage Impact
      Does TI have data on how different solder coverage percentages on the exposed thermal pad affect?

      • Thermal dissipation efficiency
      • Buck converter performance (e.g., efficiency)
      • USB switch functionality

      For example, is there a performance degrading data available for varying levels of solder coverage (e.g., 90%, 70%, 50%)?

    2. Recommended Criteria for Solder Coverage
      Is there a minimum solder coverage percentage below which performance might be significantly degraded?

      Are there specific tests or validation that can be applied to ensure sufficient solder coverage?

    Many thanks,

    Peter Wu

  • Peter,

    For the USB switch, if the quality of the ground is reduced, then more of the RF energy will be lost into the ground resulting in higher insertion loss and lower crosstalk immunity.

    The thermal and buck performance changes, I will need to reach out to other experts because this is outside of my area of expertise.

    I will work to get you an update early next week.

    Regards,

    Chuck

  • Hello Chuck,

    Thanks to your reply. I wanted to kindly follow up this topics. I understand that you needed to reach out to other experts, and I just wanted to check if there’s been any progress or additional information since your last message. Thank you.

    Many thanks,

    Peter Wu

  • Hello Peter,

    Chuck is currently out of office until after Christmas, so we will get back to you next week. Happy holidays!

    BR,

    Seong