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TPS546D24A: SMB Alert geting Asserted on Power UP

Rohith Banoth
Prodigy 30 points
Part Number: TPS546D24A

Tool/software:

Hi

We are using TPS546D24ARVFR in our design.

On power Up we observe that SMB Alert pin is getting asserted (driven low).

It is recovered on clearing the faults by writing into the register (0x3).

 

Below is the register dump on power UP when SMB Alert is asserted.

 

Can you please help on understanding the reason for the SMB Alert assertion

  • 0
    TI__Mastermind 31030 points

    Hello, 

    Please check the value of the register below to see which is causing the SMB_ALRT (Table 7-4. Fault Protection Summary)

    Thanks

    Tahar 

  • 0 in reply to Tahar Allag
    Prodigy 30 points

    Hi Tahar i see the fault protection summary registers are to define the fault and warning limits. But based on the snap of the register dump shared earlier i dont see any status registers that lead to the SMB alert

  • 0 in reply to Rohith Banoth
    TI__Mastermind 31030 points

    Hi Rohit, 

    did you see any reset or restart in the process, may be it get reset as consequence? 

    Can you try to use the mask feature on the FAULT OR WARNING to see which masked fault is triggering the Alert pin. basically scann tru all the fault and see where the ALERT goes away. 

    Thanks!

    Tahar

  • 0 in reply to Rohith Banoth
    TI__Expert 8166 points

    Hi Rohith,

    In addition to Tahar's request, could you please capture the oscilloscope waveforms for the SMB_ALRT, PMB_CLK, VDD5, and VOUT? This will help us understand the timing of the power-up sequence that triggered the SMB alert.

    Additionally, I’d like to know if this issue occurs during every power cycle and whether it is happening on any specific rail.

    Thank you,
    Tomoya

  • 0 in reply to Tomoya Ide
    Prodigy 30 points

    below is the requested capture and it is observed on every power cycle .

  • 0 in reply to Rohith Banoth
    TI__Expert 8166 points

    Hi Rohith,

    A likely reason for the SMB_ALRT signal going low is that the PMB_CLK signal is low while VDD5 is high and the PMBus is active. This may lead the device to detect a clock low timeout, lasting between 25 and 35 milliseconds. Please try bringing the PMB_CLK pull-up high before or when VDD5 is activated, and see if this helps resolve the issue.

    Thank you,
    Tomoya