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LM27762: Design Considerations for LM27762 to Power OPA928 via Dual Supply

Part Number: LM27762
Other Parts Discussed in Thread: OPA928

Tool/software:

I am working on requires powering an op amp (OPA928) via dual +/- 3V DC supply with low noise. I am constraint to a single power supply channel. This is my first time trying to design a power supply circuit so I read the technical article “The Top Three Ways to Split a Voltage Rail to a Bipolar Supply” from TI and found that the LM27762 seemed to be a good option for my needs. I spent the day reading the datasheet and tried using the WEBENCH tool as the datasheet suggested, but when I input the LM27762 in the search bar it cannot “find” the part. Additionally, there is not a TINA TI macro for me to test the IC. As such, I am attempting to configure this IC with the information available in the datasheet and was hoping to get some feedback and clarify a few points for the design of this IC for my project needs.

Using the Simplified Schematic above as a reference for my inquiries. As I am aiming for low noise and ripple, I used Fig 1&2 to select my VIN and IOUT to be 3.7 V and +/- 80 mA, respectively. My VOUT+ and VOUT- is intended to be 3 V and -3 V, respectively. I picked resistors R1, and R3 to be 115 kΩ (for R2 = R4 = 75 kΩ) based on the equations provided in the datasheet and ensuring R2 and R4 50kΩ to attain my wanted VOUT+ and VOUT- . From these parameters and knowing the expected power dissipation of the IC (PD) to be 97 mW which is well below the max power dissipation for safe operation at 25°C (PD-max 1.6 W). As I will be operating with fairly low current (I think) the capacitor values CCP, CIN, C1, COUT+ and COUT- I plan on using are 4.7 uF, 4.7 uF, 1 uF, 2.2 uF and 2.2 uF respectively.

1. My main question is with respect estimating the necessary headroom (i.e., selecting VIN, OUT+ and OUT-) appropriately. The datasheet mentions I can estimate the headroom with the maximum load current and charge pump output resistance (RCP). I feel comfortable extrapolating RCP from Fig. 4, however, I can’t seem to grasp how to estimate/quantify the maximum load current. How do I estimate this max load current? And once I do have this value, do I just use Ohms law to determine the headroom?

2. My second question is with respect to selecting capacitance values for C1 as I am currently simply using what the datasheet specifies for the quoted electrical characteristics. Is there an equation I can use for the selection of C1?

Apologies if any of these inquiries are mundane/common knowledge in power electronics. I have not acquired formal education in this are yet.

Thank you for taking the time to read this post, I appreciate any insight or design regarding my use of the LM27762.

Best,

Cam

0753.lm27762.pdf

Common PSU Inverter App Notes from TI.pdf

  • Hello Camille,

    thanks for reaching out in E2E and for your interest in our products.

    There is a LM27762 PSpice Transient Model available under the "Design tools & simulation" section of the LM27762 product web-page.

    You can use this model package to simulate the operation of the LM27762 in free PSpice For TI simulator.

    To your questions:

    1. The maximum load current is mainly determined by the OPA928 circuitry. You could use the PSpice model of the OPA928 to simulate your circuitry first and determine the current consumption from the simulation. Then you can read the RCP from Figure 4 of the LM27762 datasheet as you mentioned. It can be understood as an average resistance (averaged charge transfer of the switching cycles). But you should also consider the LDO's dropout voltage from Figure 3. From the functional block diagram in section 7.2 you can see that the positive output consists of an LDO only and for the negative output an LDO is in series to the charge pump. However you can also get a feeling for the headroom requirement from Figure 5 and 6. Lets assume a max. current consumption of 10mA the OPA928 (if it is just one) then you should be on the save side with the 3.7V input voltage.

    2. The main concern on the capacitor C1 is its ESR (Equivalent Series Resistance). It is specified in the capacitor datasheet. You can do some calculations with Equation 2 of the LM27762 datasheet, but I think you don't have to be worried too much about it when you use SMD Multi Layer Ceramic capacitors with an X7R or X5R temperature characteristic as recommended. I think in general you just can follow the application example in Table 2 of section 8.2.1 in the datasheet.

    Let me know if you have any question.

    Best regards,

    Andreas.

  • Hi Andreas,

    Thank you very much for the thorough answers and feedback.

    I will spend the day simulating my OPA928 to determine the load current draw for my application and estimate the headroom. I agree with you that I don't expect large current consumption (>100 mA) from the OPA928 but I'd like to double check to be sure. 

    Regarding C1, the application example in in Table 2 does not specify a value for C1.

    However, I gather from your explanation that we want to keep ROUT from equation 2 to be as low as possible? To do this we want both C1 to be "large" and its corresponding ESR (and ESR of the CP capacitor) to be as low as possible. Is there a general rule of thumb ROUT value I should aim for?

    I appreciate you taking the time to read this and provide suggestions.

    Best,

    Cam

  • Another follow-up,

    I spent the day learning a bit of PSCPICE to test and measure load current of the OPA928 and test out the LM27762 as you recommended. Things went relatively smoothly with the OPA928, I did a transient analysis and measured the current at each supply rail (V+ and V-). Unless I am misinterpreting the simulation results below... I expect the OPA928 load current to be no more 275 uA (the quiescent current) +/- 60 nA. The latter is due to the current source connected at the inverting pin switching from high (60 nA) to low (0 nA). 

    As this is such a low load current need, I can only really extrapolate RCP form fig. 4 to be 200Ω... and from fig. 3 it seems like there will be practically no LDO dropout voltage at that low of a current draw.

    I tried running the LM27762 to test the outputted voltages through a transient analysis as well. (Although probes are not shown in circuit below, there were two voltage probes placed at each OUT node.) But I keep getting a convergence error when trying to run the simulation and I am not sure how to resolve this issue. Do you have any insight as to how to properly simulate the output of the IC? I want to use a transient analysis to see the output ripple and play around with the capacitance values to see how the output ripple changes. I have my PSPICE file inserted below.

    LM27762_Test-PSpiceFiles.zip

    Appreciate any advice. If my issues with PSPICE should dealt in a separate forum post, please let me know.

    Best,

    Cam 

  • Hi Camille,

    thanks for the update.

    At such low load current you don't have to worry much about voltage drop at the internal resistance of the charge-pump and at the LDO.

    Sorry you are right there was no recommendation for C1 in the Application Example. Section 8.2.2.5.3 in the datasheet is giving some advice for C1. Basically you are OK with the default C1=1uF. You can also take a look at the BOM of the LM27762EVM to get some suggestions for capacitor part numbers (also in respect to ESR).

    For your PSpice simulation of the LM27762, I think it would be easiest to use the existing STARTUP_SIM schematic of the model package and modify the input voltage, EN voltage, FB dividers and add load resistors according to your use case.

    Let me know if you need any help.

    Best regards,

    Andreas.

  • Hi Andreas,

    Thanks for following-up.

    Thank you for sharing the evaluation board document for choosing capacitors, as this will greatly when I make my own BOM.

    I followed your advice regarding testing the LM27762 using the pre-existing PSPICE files. When playing around with the circuit, I noticed that when I change the EN- pin to a DC voltage source rather than a pulsed source, it seems to "break" the simulation (i.e., OUT- does not produce a negative voltage). Based on my interpretation of the datasheet, I though I could power both the EN+ and EN- pins with a DC voltage source. Am I misinterpreting something here? I attached some images below showing the simulation results.

    Above is when EN- is left as a pulse source.

    Above is when EN- is connected to DC voltage source.

    Appreciate any feedback on this. I am happy to see the LM27762 simulation works with the OPA928 with little to no dropout as you predicted. 

    Thanks,

    Cam

  • Hello Camille,

    it is quite common that these switched regulator simulation models need some initialization from a settled state (in most cases 0V).

    Alternatively you could connect EN+ and EN- to VIN and use a pulsed voltage source with some delay to supply VIN. It is still like a DC voltage supply, but it is switched on. Actually in the real application you also have to switch on the supply at some point.

    Anyway, this behavior is simulation model specific and the startup of the real IC is usually absolutely uncritical.

    Best regards,

    Andreas.

  • Hi Andreas,

    Thanks for confirming that the real/physical EN pins of the IC can be powered with a DC voltage without the delay required in the simulation model. I think I have everything I need to move forward with my project.  

    Thank you very much for your time and patience!

    Best,

    Cam

  • Hello Camille,

    thanks for your feedback. It was a pleasure to help you.

    Then I will close this thread.

    Best regards,

    Andreas.