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TPS552882-Q1: Layout and schematic check. 12V 10A

Matthew Pole
Intellectual 350 points

Part Number: TPS552882-Q1

Tool/software:

Hey,

I was wondering if someone could check over my schematic and layout to see if there are any improvements that may help the operation of the device and/or reduce EMI.

The device is to be used with a 9-36V input, 12V output. Allow up to 10A however the use case is that this feeds multiple switches for inductive loads with will have 5A kick in for <500ms then 1A continuous.

Schematic:

3D:

Top layer:

Inner 1 GND:

Inner 2 GND:

Bottom Layer:

And this is being fed by my input circuit:

How does this all look? ALso, in the EN pin that is driven by my MCU suppossed to be pulled down to PGND or AGND? I have it to AGND currently!

Thank you in advance!

  • 0
    TI__Mastermind 18290 points

    Hi Matthew,

    Thank you for reaching out. Glad to see that your design is very good.

    1. Recommend to pull EN to AGND.

    2. Recommend to change L1 to 4.7uH. 8.2uH will lead to low right half plane zero. This will limit bandwidth and transient response.

    3.Can you help provide part number of C69-C71 to calculate loop parameters?

    4.Maimum output current is 10A in total, right?

    About the layout:

    1.Recommend to put C67 more close to IC.

    2. One or two via is enough for AGND plane. For the inner layer1, reserve only one via position. Make sure the GND is as complete as ppossible,

    3.Put 4 vias in VCC cap GND since there is current flow it.

    4.Enlarge the Vout and GND plane in bottom layer for better thermal performance.

    Regards,

    Mulin

  • 0 in reply to Mulin Yuan
    Intellectual 350 points

    Hey Mulin,

    Thank you for the reply!

    1. Recommend to pull EN to AGND. - OK, I will keep it as is then to have this use AGND for the pull down reference.

    2. Recommend to change L1 to 4.7uH. 8.2uH will lead to low right half plane zero. This will limit bandwidth and transient response. - Changed. I have used a 7443330470 instead:

    3. Can you help provide part number of C69-C71 to calculate loop parameters? - C69 - C0603X103K4RECAUTO
    C70 - C0402C150J4GACAUTO
    C71 - GRT188R61C475KE13D

    4. Maimum output current is 10A in total, right? - Yes, the max allowable current should be 10A. Although the max actual current will be 6A for a short burst when closing contactors.

    About the layout:

    1.Recommend to put C67 more close to IC. - Do you mean a differnt cap as C67 is one of the bulk caps?

    2. One or two via is enough for AGND plane. For the inner layer1, reserve only one via position. Make sure the GND is as complete as ppossible. - OK. I have lowered the amount of vias, see new images below. I don't what you mean for inner layer 1? Do you mean just have a plane cutout around 1 via? Is this on both sides?

    3.Put 4 vias in VCC cap GND since there is current flow it. - OK, I have added another 2 which are in the images below

    4.Enlarge the Vout and GND plane in bottom layer for better thermal performance. - I can't go much bigger on VOUT but GND will be flooded on top and bottom layer once on the PCB do the GND area will be large

    Thanks again for the support!



    Also, on a slighlty seperate note. I may have just found out what I was potentially having issues on my previous board. I was not cutting out the AGND section from my overall PCB GND on the bottom layer! Would this cause issues when enabling a 5A load on the output?

  • 0 in reply to Matthew Pole
    TI__Mastermind 18290 points

    Hi Matthew,

    I will look into this later.

    Regards,

    Mulin

  • 0 in reply to Mulin Yuan
    Intellectual 350 points

    Hi Mulin,

    That would be great, thank you very much!

  • 0 in reply to Matthew Pole
    TI__Mastermind 18290 points

    Hi Matthew,

    The first schematic and the second schematic that you provide are not the same. The annotation of each parts are different. So the part number of the output caps you provide is not right. 

    Regards,

    Mulin

  • 0 in reply to Mulin Yuan
    Intellectual 350 points

    Ah apologies, I didn't realise I updated annotations! The output caps are GCM32EC71E226KE36K

  • 0 in reply to Matthew Pole
    TI__Mastermind 18290 points

    Hi Matthew,

    According to the output caps, current compensation parameters are ok.

    Matthew Pole said:
    1.Recommend to put C67 more close to IC. - Do you mean a differnt cap as C67 is one of the bulk caps?

    I mean the 0.1uF cap before you update the annotations.

    Matthew Pole said:
    I don't what you mean for inner layer 1? Do you mean just have a plane cutout around 1 via? Is this on both sides?

    I mean the inner 1 GND is cut off by too many AGND vias. No need to cut off the GND plane in Inner 1 GND.

    AGND vias are too much here. One or two is enough.

    Matthew Pole said:
    Also, on a slighlty seperate note. I may have just found out what I was potentially having issues on my previous board. I was not cutting out the AGND section from my overall PCB GND on the bottom layer! Would this cause issues when enabling a 5A load on the output?

    AGND may have some noise, but it is not that serious. Basically the signal pins are seoerated.

    Regards,

    Mulin