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LM5060-Q1: Schematics review and how the Rsense works in this scenario

Nidhi udhayan I
Prodigy 10 points
Part Number: LM5060-Q1
Other Parts Discussed in Thread: LM76202-Q1, LM5060

Tool/software:

Hi,

I have a worked a schematics using LM5060-Q1 for the below mentioned specification, does this looks fine or any improvement needed in the design.

Design specifications
Input voltage 9-16V
OVP typical 18V
UVP typical 9V
Current max 1A

The output of LM5060-Q1 goes to a Buck regulator. End application is a rear view camera used in an automobile

Also we are testing the boards as per,

ISO 7637-2 Pulse 1(-150V) and Pulse 2a(+112V)

ISO 16750-2 Load dump Test B with centralized load dump suppression.

Also ,I need some clarification regarding the working of the sense pin and the calculation of Rsense for understanding purpose, the use of Rsense is to limit the output current or any other.

  • 0
    TI__Guru** 105281 points

    Hi Nidhi,

    The best solution for your target specs is LM76202-Q1. please have a look and let us know.

    BR,

    Rakesh

  • 0 in reply to Rakesh
    Prodigy 10 points

    Hi Rakesh,

    Thanks for your suggestion, dimension of the IC is the actual constrain for us. So we went for LM5060-Q1, Kindly check whether the provided solution is capable of withstanding the tests and the schematics is good.

  • 0 in reply to Nidhi udhayan I
    TI__Guru** 105281 points

    Hi Nidhi,

    Centralized load dump suppression limits the voltage surge to 35 V so TS2 gets stressed as it is 18V rated. Replace it with 36V rated TVS.

    FET Q2 orientation (drain and source) should be reversed. 

    Add 22 Ohm in series with C15 to limit the discharge current into the GATE pin of LM5060.

    By the way, what is the concern with the dimension of the  LM76202-Q1 ??

    BR,

    Rakesh