TPS22811: Power cycling

I am experiencing what may be a similar issue.  We are using the TPS22811 to switch a small cooling fan (+12VDC @ 0.9A).  When the +12VDC (sourced from a SynQor brick) initially comes on, the switch closes and the fan runs.  When we subsequently cycle the EN_OVLO pin to shut down the fan it never recovers.  The +12VDC remains present at all times.  We have disabled the current limit by connecting IMON to ground and have tried various slew rates by changing the DVDT capacitor.  We have also tried various capacitors on the output - all to no avail.  The part turns on and off when we use a 1A resistive load, but stubbornly refuses to turn back on with a fan load.  We have a reverse Schottky diode across the output.  There is 220uF of capacitance across the input.  It seems like there have been other threads that allude to turn on recovery issues.  Can anyone help?  Thanks!

Hi Phani,

Can you confirm which pin you pulled high for power cycling. Is it EN/UVLO or ENb/OVLO?

If there is higher cout during startup, the inrush current will be higher and may result in device limiting the current during the startup. If the power dissipation is very high while limiting the current, the device may perform thermal shutdown.

Best regards,
Arush

Hi Vincent,

Again, I would like to confirm the pin you are using for power cycling. Is it EN/UVLO or ENb/OVLO. The power cycling can only be done by Vin or EN/UVLO pin and cannot be done by ENb/OVLO.

Vincent Spataro said:

We have disabled the current limit by connecting IMON to ground and have tried various slew rates by changing the DVDT capacitor.  We have also tried various capacitors on the output - all to no avail. 

I understand your frustration. We have a design calculator. It might help you in verifying if the dvdt value and load will result in glitch free startup. Can you check that. I think that will help you. Also can you share your schematic/configuration, load and waveforms of issue. 

Design Calculator: https://www.ti.com/tool/download/SLVRBL4

Best Regards,
Arush 

Hi Arush,

As per the datasheet, it mentions ~EN/OVLO, and we have followed this in our design. My understanding is that this pin can be used to turn the output on and off. Is there any additional meaning or nuance to this function that we should be aware of?

Additionally, is there any errata or known issues related to this behavior? We’ve already built the board according to the datasheet, and we’re currently not able to turn it on back using ~EN/OVLO. Similar story to Vincent, we also tried different slew rate and current limits values. 

Looking forward to your insights.

Hi Phani,

Power cycling can only be done using Vin or EN/UVLO pin and not from ENb/OVLO pin. Can you try this again with EN/UVLO pin cycling.

Best Regards,
Arush

Hi Arush, Thanks for the quick reply!  We are exercising Pin 2 EN/OVLO.  The intent of this circuit is to turn off our fan when the input line drops below 16VDC, so that our fan does not continue to run and draw power during our 100msec power hold-up period.  In order to accomplish that, we use a 3.3V DCFAIL_P signal on EN/OVLO, which does indeed turn off the fan.  If the input power drops to zero (as is usually the case) and then comes back, we have no issue - the fan starts up again.  However, if the input voltage drops to say 15VDC and then returns to its nominal 28VDC (admittedly a corner case), the fan will not restart.  Note that at 15VDC input, our SynQor brick continues to supply an uninterrupted 12VDC to the TPS22811.  According to the data sheet, Page 16, " After the voltage at the EN/OVLO pin crosses the OVLO rising threshold Vov(R), the device turns off power to the output.  Thereafter, the devices wait for the voltage at the EN/OVLO pin to fall below the OVLO threshold Vov(F) before the power is turned ON again."  What I am suspecting, from your reply and the graph Figure 7-3, is that the voltage going low on EN/OVLO is a necessary, but not sufficient, condition for turning the TPS22811 on again.  I suspect that you need to pull EN/OVLO low and also remove power from the TPS22811, otherwise the device just latches off.  The data sheet wording is not entirely clear on this point (at least to me).  So, did I get this response above right?  I think you are saying that if I use the EN/UVLO input (Pin1) to turn the TPS22811 ON and OFF, I will not see this latch-off problem.  Do you agree?  I'm thinking that maybe Phani is going down the same road.  Thanks again!

Hi Arush

Vincent and I ended up in similar problems but we did a modification to our boards using UVLO pin for power cycling and it is working for us.

Why is this not mentioned in datasheet that ~EN/OVLO cannot be used for power cycling ?

My understanding is Enable pins can be used for turning on and off. Any datasheet amendments are you planning to do in order to avoid confusion ?

We need to re-spin boards because of this issue. Some more clarity on power cycling in the datasheet would be appreciated so that people does not end up like us !

Hi Arush,

 EN meaning enable the output? Doe this have another meaning? What is the difference between power cycle out put and using EN? What is the actual purpose of EN? As per datasheet both of this pin can be used EN purpose. Does that feature changed in new versions and datasheet I am looking is older one?

Hi Phani,

I understand your frustration but nowhere in the datasheet it is mentioned that power cycling can be done using OVLO pin. I will take your feedback and bring it in front of team responsible for datasheet.

Another thing I would point out is power cycling can also be done using Vin pin. Just wanted to bring this to your attention. Not sure if this will help in preventing re-spin.

Also power cycling using Vin or EN/UVLO is common across all the TI eFuse portfolio and from what I know, across the competitors also.

Best Regards,
Arush

Hi Grittin,

Yes, EN is also Undervoltage lockout pin (UVLO). Similarly ENb is also Overvoltage lockout pin (OVLO). When using a resistive divider from Vin to these pins, based on the selected resistor values, you can set the undervoltage and overvoltage protection thresholds.

Internally both pins have comparator and if these can be used as EN or ENb but only UVLO or low VIN signal is internally used for resetting the device.

Best Regards,
Arush

Hi Arush

The name is ~EN/OVLO that means it enables from OFF to ON and vice-versa. 

I appreciate if you take it forward and avoid the confusion on this for designers who are going to use this in future.

Also May I know the reason what happens if I try power cycling using OVLO pin ? Will it activate QOD ?

If it does not activate QOD then how discharge happens ? During the discharge which shut-down happens and is any latch triggered ?

And what are the possible ways to clear the latch ?

As we are using this IC and we are at critical stage of our design and no where in datasheet there is info regarding discharge during OVLO, all these info helps us design/re-design better. 

Your help is greatly appreciated !

Arush,

I am not sure how to make it more clear...  Why chip is going to latched protection when we use ENb ? I could not see any reason for thermal shutdown or short circuit protection  to kick start the latched protection. What is the other reason which is not in the datasheet causing it? During OV condition, output turns off and expected to return  back to normal once it is out of OV right?  We are intentionally making a OV to turn off the output and expecting it to turn on back when OV pin see a normal voltage. Are we missing something?

ENb high = Output is OFF ( inside Mosfet is OFF)

ENb 0V = Output is ON  ( Inside Mosfet is ON)

Hi Phani,

Phani Bhushan Nagisetty said:

The name is ~EN/OVLO that means it enables from OFF to ON and vice-versa. 

That's true, it will turn off the device but internally this signal cannot be used for resetting the device.

Phani Bhushan Nagisetty said:

I appreciate if you take it forward and avoid the confusion on this for designers who are going to use this in future.

I have noted this down in my datasheet changes list but will need to get it verified from systems team. 

Phani Bhushan Nagisetty said:

Also May I know the reason what happens if I try power cycling using OVLO pin ? Will it activate QOD ?

QOD is controlled using EN/UVLO pin. No, QOD won't be activated with OVLO pin.

Phani Bhushan Nagisetty said:

If it does not activate QOD then how discharge happens ? During the discharge which shut-down happens and is any latch triggered ?

ENb/OVLO will turn off the mainFET. The output voltage will discharge through the load. The FET is off so Vout will be floating from eFuse side.

Phani Bhushan Nagisetty said:

And what are the possible ways to clear the latch ?

Here I am assuming you mean latch which happens after any fault. It can be cleared by cycling Vin or EN/UVLO pin.

Phani Bhushan Nagisetty said:

As we are using this IC and we are at critical stage of our design and no where in datasheet there is info regarding discharge during OVLO, all these info helps us design/re-design better. 

No issue, I also don't want you to go through re-spin. Please feel free to ask any questions. I would recommend go through datasheet once (especially section 7 and 8). Also for layout check section 10. 

Best Regards,
Arush 

Hi Grittin,

Grittin James said:

Why chip is going to latched protection when we use ENb ? I

I think there is some confusion here. ENb is not a latching fault. When the Over voltage state goes away, the device will start again but TSD and SCP are latching faults. I understand the need for auto-retry. We have similar device from this family which provides option of auto-retry. It is called TPS25981. 

Grittin James said:

During OV condition, output turns off and expected to return  back to normal once it is out of OV right?  We are intentionally making a OV to turn off the output and expecting it to turn on back when OV pin see a normal voltage. Are we missing something?

This is correct. 

Grittin James said:

ENb high = Output is OFF ( inside Mosfet is OFF)

ENb 0V = Output is ON  ( Inside Mosfet is ON)

Yes. The above discussion with others was about removing the latching faults using OVLO pin which is not possible. 

Can you create another thread with this part number. I can respond to your exact query there. I am trying to keep all the replies separate but the discussion is getting mixed.

Best Regards,
Arush

Hi Arush

Thanks for the detailed explanation.

As I told in the start " I am using TPS22811 in our design for 12V application. We have around 500uF capacitance on the output of TPS22811. If I just pull high the EN_OVLO pin for power cycling the IC is not turning ON again."

The IC is going into latch mode and when I toggle EN pin or power cycle , the switch is turning ON.

We need to know the reason why this is happening ?

Regards

Phani Bhushan

In our case the OV pin is pulled to around 3.8V and then going to zero after few seconds. The IC is not turning ON even when the OV pin going to zero volts. Do you see any reason we can go to TSD if the board temperature is around 50 deg C ?

Hi Phani

Oh, so are you saying that turning off the device using OV pin is causing latching and you are not trying to removing latching by toggling the OVLO pin.

This is not expected. Do you have any waveform? How are you providing OV pin high. Are you increasing Vin and have a resistive divider or OV pin is connected to external supply.

Best Regards,
Arush

Arush Gupta said:

saying that turning off the device using OV pin is causing latching and you are not trying to removing latching by toggling the OVLO pin.

EXACTLY

Arush Gupta said:

This is not expected. Do you have any waveform? How are you providing OV pin high. Are you increasing Vin and have a resistive divider or OV pin is connected to external supply.

We have one more circuit which drives OV pin. The other circuit(push button reset) outputs 12V through a resistive divider which gets divided to around 4V.

We can see that switch is going off at that instant but when it comes back to zero volts , the IC is not turning ON.

The push button reset circuit is working fine.

Legend for the waveforms : 

12V - output voltage of the switch

12V-sync  - input voltage of the switch

ovlo - ovlo pin of the switch

i- 12V - Current through the switch

Hi Phani,

Can you share your schematic (TPS22811 and controlling circuitry and load).

Best Regards,
Arush

Arush , 

I am not supposed to share the schematics but I am sharing you the block diagram of the application.

Please let us know why it is latching.

Hi Arush

Did you find the root-cause. We were stuck on this from more than a week now.

Your quick response is appreciated.

Thanks

Phani Bhushan

Hi Phani,

The expected behavior here is ovlo when taken below falling threshold, load switch should recover. Now as this isn't happening here. I would suggest some basic things to rule out different dependencies.

• Use external UV and OV inputs to verify if the device is working fine or not. If this is failing, replace the device and recheck.
• Use resistive divider for UV and external OV. Similarly your OVLO circuitry and external UV inputs. depending on which one is failing, you can pin point to pin which is causing this issue.
• resistive divider for UV and OVLO circuitry. I understand that this is not working hence the issue. I hope above two will help in pin pointing if this is really related with UV or OV pin or something else. 

I did not mention anything about IMON and dvdt cause you have already tried with different values. 

Best Regards,
Arush