• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 62 subscribers
  • Views 182 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TPS7A26: A phenomenon in which the output voltage is not 0V when VEN=0

TPS7A20: A phenomenon in which the output voltage is not 0V when VEN=0

sg han
Prodigy 30 points
Part Number: TPS7A20

Tool/software:

hello. In this project, the circuit was constructed using TPS7A20.

The current consumption of the load connected to the TPS7A20 does not exceed 10mA.

I am trying to turn the TPS7A20 output ON/OFF by controlling the VEN on the FPGA.

When VEN=0, Vout is output as an abnormal voltage instead of 0V(1.55V)

I would like to know why this phenomenon occurs and what solutions might be available.

Due to internal security policies, I cannot provide the complete circuit. Therefore, I am attaching a portion of the schematic that includes the TPS7A20.

The attached oscilloscope capture shows the state of the board when power is applied. (Green = VIN(5V), Blue = VOUT(1.55V), Yellow = VEN).

I suspect that the issue might be that, despite VEN being 0, the output is showing 1.55V, which seems to be the UVLO voltage being connected to the output. Please review this as well.

For additional information, when VEN is High, the output is 2.5V (normal operation).

  • 0
    TI__Genius 11010 points

    Hello,

    I am working on finding a solution to this problem. I realize that this is the second problem of this type which you have observed recently, both with different devices.

    Could you please let me know if there are commonalities in these circuits/ testing methodologies which may be causing these issues? Meanwhile I will debug with the information you have sent.