TPS3430: WDI input while WDO is low

Hello Hirotsugu,

Are you able to provide the schematic for this design? Is the Trst also 10s for the late fault as well?

Jesse 

Hi Jesse,

A simple circuit diagram and the phenomenon are attached.

I have attached a simple circuit diagram and an example of the phenomenon.
Normally, WDI is not input while WDO is low, but I confirmed this phenomenon while debugging.
The data sheet does not describe what happens if WDI is input while WDO is low, so please tell me what behavior occurs.

There are older SVS products with WDT function that latch off when a similar operation is performed, but what happens with the TPS3430?

Best regards,

Hi Hirotsugu,

Please refer to to table 5-1 of the datasheet for the behavior.

For the the issue, I will have to double check with my EVM. Do you happen to have the evm for this device?

https://www.ti.com/tool/TPS3430EVM

Jesse 

Hi Jesse,

I don't have the evm. Even if I order one now, it will take a few days.

Could you please check with your EVM?

Best regards, 

Hi Jesse,

Thanks for testing.
What is the Trst time setting (CRST terminal)?

Could you please test again with the CRST terminal open?

Best regards,

The CRST is 10nF, default on the EVM board, which gave me roughly 32.6ms.

I will test with CRST open and provide data end of day.

Jesse 

Hi Jesse,

Thanks for testing.
I'll check customer's system again.

Best regards,