CSD16301Q2: Leakage into drain when off in PSpice for TI

Hello Klaas-Jan,

Thanks for your interest in TI FETs. The PSpice models for our FETs are not correlated to the measured leakage data. However, it should not be orders of magnitude higher than what is specified in the datasheet. Can you share your PSpice simulation? Can you also include the VGS waveform in the plot?

Best Regards,

John Wallace

TI FET Applications

MosfetLeakage.zip

Here is the PSpice simulation.

^pulse up

^pulse down

In yellow Vgs

I do not understand what you mean with:

"The PSpice models for our FETs are not correlated to the measured leakage data. " and then however..

This part simulates much better CSD87502Q2, could it be the output capacitance not being linear over time?

If so, how can I calculate this from the datasheet?

Hi Klaas-Jan,

Thanks for providing additional information. When TI developed the PSpice model for a FET, the measured test results are correlated to the simulation results and the model may be adjusted to get the best fit to the measured results. This is done for many of the parameters and curves in the datasheet. There is no correlation or comparison done for leakages, IGSS and IDSS. Therefore, it is unknown how closely the leakage simulated by the models matches the measured data. In general, the models are close but usually lower than the actual device performance.

I'm trying to understand what the circuit is doing. The voltage generator V3 is driving the gate of the FET and the inputs to the NAND gate which is being used as an inverter. The output of the NAND gate drives the R-C to charge the capacitor when the input is low and the FET is off. When the input is high, the FET discharges the capacitor. I'm not sure why there is drain current flowing when VGS ~ 0V. Still trying to figure that out.

The FET capacitances are non-linear vs. VDS as shown in the datasheet but I don't think that should affect the simulation. Give me some more time to look at this and I'll get back to you when I have more information.

Best Regards,

John

Yes, that is what the circuit is doing, I need the capacitor of the RC filter to discharge asap so that the RC filter is ready quickly to generate the next pulse.

Thnx John! I await you reply!

Hi Klaas-Jan,

I've tried the simulation and there is still current flowing in the FET but I'm not certain why and if it is real. A DC simulation gives the desired results with very tiny drain leakage current when the FET is OFF. I've tried some different FETs like the CSD15380F3 which behaves better in the simulation. I'll continue working on this and provide an update when I have more information.

Thanks,

John

Thanks for your help. That's interesting what you say about the DC simulation, i have noticed that in Pspice there are often seperate settings for AC and DC simulation, maybe also in de spice model. Yeah I have dropped in random TI mosfets and it seems that many exhibit this leakage. The build in small signal (prefix: BSS..) behave very good but again the IRF ones don't. And i noticed the BSS ones have a very small output capacitance. This is how i found the CSD87502Q2 because it also has small output capacitance (50pf instead of 200+pf) but is still very fast.

Also have you noticed that the leakage current goes both to the gate and the source, the current through the source is double that of the gate

I think the problem can be partially explained by the output capacitance of the CSD16301Q2. It has a max of 215pf according to the datasheet at VGS=0, so it would compete with the RC filter if its modelled as max. But, if i remove the mosfet and replace it with a 220pf capacitor. the RC filter still is double as fast as with the mosfet, so this doesnt explain all. Could it be that the output capacitance is modelled wrong?

Hi Klaas-Jan,

I think you're correct about the Coss affecting the charging time and causing current to flow as the timing capacitor is essentially in parallel with Coss. I think a smaller, low capacitance FET will perform better without as big an impact on the timing. The CSD15380F3 is very low capacitance (8.1pF typical) with 4Ω max on resistance at VGS = 2.5V (should be lower at VGS = 3V). It performs well in the simulation and I think it should be adequate for fast discharge of the timing capacitor. Let me know what you think.

Thanks,

John

Hi, yes, I already have put it in my final schema and its much better. Still a mistery why the capacitance of the first mentioned mosfet does not simulate like the datasheet would specify. But, if you want, i am quite happy with the mosfet you found and i think i will proceed and put it in my final design.