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Tool/software:
Our OBU board recently had some cases of TLV62090 and TPS63020 damage.
Our two TPS63020 and two TLV62090 are powered by one power supply. Currently, we suspects that there may be problems in phase stability when the four chips are connected in parallel, leading to eos risk.
Could you please evaluate the phase stability of 4 chips in parallel state? The input of the 4 chips is combined together.
Hi Cao,
Could you share more details about this damage? both four device are damaged? what kind of damage you observed?
What do you mean about phase stability?
Regards
Tao
Mainly want to check the phase margin, loop stability, loop gain, please help check these characteristics of our design have any problems?
Hi Cao,
From my side, would like to say that no loop issue found about TPS63020 part.
Regards
Tao