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BQ25120F3A: Clarity need about layout

PSG_4
Intellectual 640 points
Part Number: BQ25120F3A


Tool/software:

Hi 

There is one clarity need in layout  about connection of  BQ25120F3A  pin A5 (PGND) and SYS output filter capacitor GND pin. 

I have provided pad on via on both pin A5 and sys filter output capacitor GND  pad as shown in picture. Both vias directly connected to continuous  GND layer at layer 2 ( marked as green circle) . Also both pins shorted at Layer 1 ( marked as Blue line) .

Is this connection topology is okay  ? Let me know whether I need to remove the connection trace at L1 ( blue line) .

Regards

PSG_4

  • 0
    TI__Mastermind 18520 points

    Hi PSG_4,

    I recommend placing the NETL3_1 pad closer to the pin. This node is the switch node of the buck, and the larger the pad the more noise it is likely to cause. Keeping this polygon small and close to the source pin is recommended. By rotating the inductor you can reduce the footprint of that path.

    Best Regards,

    Juan Ospina

  • 0 in reply to Juan Ospina
    Intellectual 640 points

    Hi Juan,

    Inductor placement has done as per TI suggestion in datasheet  shown  below .

    My original question is whether I need to keep or delete connection between A5 pin (PGND) and SYSEM output filter capacitor Ground connection at Layer  L1 ( indicated as Blue line in initial  question) . Already both pins are directly connected at Layer 2 (next continuous GND plane under L1)  .

    Please comment. 

  • 0 in reply to PSG_4
    TI__Mastermind 18520 points

    Hi PSG_4,

    I understand, it is not a significant impact on the placement of the inductor, but if noise is a concern it can help reduce it.

    PSG_4 said:
    My original question is whether I need to keep or delete connection between A5 pin (PGND) and SYSEM output filter capacitor Ground connection at Layer  L1 ( indicated as Blue line in initial  question) .

    Keeping that connection would be preferable as it shortens the ground loop distance a bit.

    Best Regards,

    Juan Ospina

  • 0 in reply to Juan Ospina
    Intellectual 640 points

    Hi Juan, 

    One more further query :

    >> Keeping that connection would be preferable as it shortens the ground loop distance a bit.

    => Actually This trace  ( blue color indication) is  an additional  connection between both pins. Is this act as loop and generate any noise ? Basically I need to understand this can contribute any noise.

    Please comment .

    Regards

    PSG_4

  • 0 in reply to PSG_4
    TI__Mastermind 18520 points

    Hi PSG_4,

    I understand, the question is regarding if it is ok because of the loop created between this trace, the via, and the GND on layer 2. If this is a concern then you can remove the via under the capacitor. A direct trace from the pin to the capacitor is preferable than going through two vias and the GND layer.

    Best Regards,

    Juan Ospina